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1/90 STA310 june 2003 this is preliminary information on a new product now in development. details are subject to change without notice. 1 features n dvd audio decoder: z meridian lossless packing ( mlp ), with up to 6 channels, z uncompressed lpcm with 1-8 channels, z precision of up to 24 bits and sample rates of between 44.1 khz and 192 khz. n dolby digital (*) decoder: z decodes 5.1 dolby digital surround. z output up to 6 channels. downmix modes: 1, 2, 3 or 4 channels. n mpeg -1 2- channel audio decoder, layers i and ii. n mpeg-2 6-channel audio decoder, layer ii. z 24 bits decoding precision. n mp3 (mpeg layer iii) decoder. n accepts mpeg-2 pes stream format for: mpeg-2, mpeg-1, dolby digital and linear pcm. n karaoke system. n prologic decoder. n downmix for dolby prologic compatible. z a separate (2-ch) pcm output available for simultaneous playing and recording. n bitstream input interface: serial, parallel or spdif. n spdif and iec-61937 input interface. n spdif and iec-61937 output interface. n pll for internal pcm clock generation. frequencies supported: 44.1khz family (22.05, 88.2, 176.4) and 48khz family (24, 48, 96, 192). n pcm: transparent, downsampling 192 to 96 khz and 96 to 48khz. n pts handling control on-chip. n no external dram required n i 2 c or parallel control bus n embedded development ram for customizable software capability. n configurable internal plls for system and audio clocks, from an externally provided clock. n 80-pin tqfp package n 2.5v (for core) and 3v (for i/o) power supply. z 3v capable i/o pads . n true-spdif input receiver supporting aes/ ebu, iec958, s/pdif. z no external chip required. z differential or single ended inputs can be decoded. applications n high-end audio equipment. n dvd consumer players. n set top box. n hdtv . n multimedia pc. (*) dolby , ac-3 and prologic are trademarks of dolby laboratories. description the STA310 is a fully integrated audio decoder ca- pable of decoding all the above listed formats. encoded input data can be entered either by a serial (i2s or spdif) or a parallel interface. a second input data stream (i2s) is available for micro input. the control interface can be either i 2 c or a parallel 8- bit interface. no external dram is necessary for a to- tal of 35ms surround delays. tqfp80 ordering number: STA310 prelyminary data 6+2-ch. multistandard audio decoder
STA310 2/90 2 STA310 audio decoder pin description pin number name type function control interfaces 48 irqb o (1) interrupt signal (level), active low 47 seli2c i (2) selects the control interface (when high: serial interface; when low: parallel interface) i 2 c control interface 43 sdai2c i/o (1) i 2 c serial data 46 sclki2c i i 2 c clock 53 maini2cadr i (2) determines the slave address parallel control interface 78 - 79 - 80 - 1 2 - 3 - 6 - 7 d0 - d1 - d2 - d3 d4 - d5 - d6 - d7 i/o host data 12 - 13 - 14 - 15 16 - 18 - 19 - 20 a0 - a1 - a2 - a3 a4 - a5 - a6 - a7 i host address 21 dcsb i chip select, active low 22 r/w i read/write selection: read access when high, write access when low 35 waitb o (3) data acknowledge, active low data input interface first serial data interface (i 2 s) 37 dstrb i clock input data, active low 41 sin i serial input data 40 lrclkin i word clock for the input 42 req o handshake for the data transfer, aconfigurable by the sin_setup register second serial data interface (i 2 s) 62 dstrb2 i clock input data, active low 60 sin2 i serial input data 61 lrclkin2 i word clock for the input 63 req2 o handshake for the data transfer, active low data output interfaces 69 pcmclk i/o oversampling clock input for STA310 when generated externally dac interface 67 sclk o bit clock for the dac
3/90 STA310 68 lrclk o word clock for the dac 72 pcm_out0 o data from a prologic downmix (vcr_l/vcr_r) 73 pcm_out1 o data for the first dac (left/right) 76 pcm_out2 o data for the second dac (centre/sub) 77 pcm_out3 o data for the third dac (leftsur/rightsur) iec958 interface (s/pdif) - one output port., one input ports. 58 i958out o s/pdif signal 25 spdp i first differential input of s/p dif port 24 spdn i second differential input of s/p dif port 26 spdf i external filter 28 vdda i analog vdd for s/p dif input port 29 gnda i analog gnd for s/p dif input port status information pcm related information 54 sfreq o then high, indicates that the sampling freq. is either 44.1khz or 22.05khz. when low, indicates that the sampling frequency is either 32 khz, 48 khz, 24 khz or 16khz. 57 deemph o indicates if de-emphasis is performed. audio video synchronization 59 ptsb o indicates that a pts has been detected, active low. other signals 31 clk i master clock input signal. 36 reset i (2) reset signal input, active low. 52 testb i (2) reserved pin: to be connected to vdd 49 smode i reserved pin : to be connected to gnd rs232 interface 8 rs232rx i 9 rs232tx o plls interfaces 64 clkout o system clock output with programmable division ratio 27 pllaf i external filter for audio pll. 2 STA310 audio decoder pin description (continued) pin number name type function
STA310 4/90 notes (1) open drain (2) internal pull-up (3) tri-state pin connection (top view) 30 pllsf i external filter for system pll. power and ground 5 - 11 - 23 - 33 - 39 - 45 - 50 - 56 - 66 - 71 - 75 gnd gnd ground 4 - 17 - 34 - 38 44 - 55 - 65 - 74 vdd vdd 2.5v power supply 10 - 32 - 51 - 70 vdd3 vdd3 3.3v power supply 2 STA310 audio decoder pin description (continued) pin number name type function 1 2 3 5 6 4 7 8 9 10 31 11 32 33 34 35 36 75 74 73 72 70 71 69 68 67 66 65 55 54 53 51 50 52 60 59 58 56 57 d6 gnd vdd d4 d3 d5 gnd vdd3 rs232tx d7 rs232rx spdf pllaf vdda gnda clk pllsf vdd3 gnd vdd waitb hrstb gnd vdd pcm_out1 pcm_out0 vdd3 gnd pcmclk lrclk sclk gnd vdd vdd sfreq maini2cadd vdd3 gnd testb sin2 ptsb i958out gnd deemph d00au1225 26 27 28 29 30 76 pcm_out2 77 pcm_out3 78 d0 79 d1 80 d2 dcsb hrwb gnd spdn spdp 21 22 23 24 25 49 48 46 45 47 smode irqb sclki2c gnd seli2c 12 13 14 15 16 a4 a3 a2 a0 a1 64 63 62 61 clkout req2 dstrb2 lrclkin2 37 38 39 40 dstrb vdd gnd lrcklin 44 42 41 43 vdd req sin sdai2c 17 18 19 20 a7 a6 a5 vdd
5/90 STA310 absolute maximum ratings electrical characteristics (v dd = 3.3v +/-0.3v; t amb = 0 to 70c; rg = 50 w unless otherwise spec- ified general interface note: 1. the leakage currents are generally very small, <1na. the value given here, 1 m a, is a maximum that can occur after an electrostatic stress on the pin. 2. v> vdd3 for 3.3v buffers. 3. human body model lvttl & lvcmos dc input specification 2.7v vdd 200 ma 2 vesd electrostatic protection leakage <1 m a 2000 v 3 symbol parameters conditions min typ max unit note v il low level input voltage 0.8 v 1 v ih high level input voltage 2.0 v 1 v ilhyst low level threshold input falling 0.8 1.35 v 1 v ihhyst high level threshold input rising 1.3 2.0 v 1 v hyst schmitt trigger hysteresis 0.3 0.8 v 1
STA310 6/90 electrical characteristics (continued) note: 1. min condition : v dd = 2.7v, 125c min precess max condition: v dd = 3.6v, -20c max power dissipation introduction the STA310 is a fully integrated multi-format audio decoder. it accepts as input, audio data streams coded with all the formats listed above. 2.1 inputs and outputs 2.1.1 data inputs - through a parallel interface (shared with the control interface) - through a serial interface (for all the i 2 s formats) - through a s/p dif ( spdif or iec-61937 standards). - trough a second, independent, i 2 s (for application like i..e. karaoke mixing). 2.1.2 data outputs - the pcm audio ooutput interface, which provide: pcm data on 4 outputs: ? left/right, ? centre/subwoofer ? left surround/right surround. symbol parameters conditions min typ max unit note ipu pull-up current vi = 0v -66 0.8 m a 1 rpu equivalent pull-up resistance vi = 0v 50 k w symbol parameters conditions min typ max unit note p d power dissipation @v dd = 2.4v sampling frequecy 24khz t.b.d. mw 1 sampling frequecy 32khz t.b.d. mw 1 sampling frequecy 48khz t.b.d. mw 1 s/p dif STA310 2 i2s mmdsp+ i2c host i/f 8 pcm s/p dif ac3 dvd audio mpeg
7/90 STA310 ? data from a prologic downmix (encoder) lrclk sclk pcmclk - s/p dif output 2.1.3 control i/f i2c slave or parallel interface: the device configuration and the command issuing is done via this interface. to fac ilitate the contact with the mcu, 2 interrupt lines (irqb and intline) are available. 3 architecture overview 3.1 data flow the STA310 is based on a programmable mmdsp+ core optimized for audio decoding algorithms. dedicated hardware has been added to perform specific operations such as bitstream depacking or iec data formatting. the arrows in figure 3 indicate the data flow within the chip. the compressed bitstream is input via the data input interface. data are transferred on a byte basis to the fifo. this fifo allows burst input data at up to 33mbit/s. the input processor, which is composed of a packet parser and an audio parser, unpacks the bitstream (packet parser) and verifies the syntax of the incoming stream (audio parser). the compressed audio frames with their associated information (pts) are stored into the circular frame buffer. while a second frame is stored in the circular frame buffer, the first frame is extracted by the audio core decoder which decodes it to produce audio samples. the pcm unit converts the samples to the pcm format. the pcm unit controls also the channel delay buffer in order to delay each channel independently. in parallel, the iec unit transmits non compressed data or compressed data according to the selected mode. in the compressed mode, the data are extracted directly from the circular buffer and formatted according to the iec-61937 standard. in non compressed mode, the left and right pcm channels formatted by the pcm unit are output by the iec unit, according to the spdif standard figure 1. architecture and data flows 1 datain input data interface host interface control, status clocks 2 fifo 256 x 8 input processor circular frame buffer 3 4 core audio iec958 formater pcm unit channel delay buffer (35ms) decoder 6 7 8 iec958 (1937) out pcmout 5
STA310 8/90 3.2 functional diagram figure 2. audio decoder top level functional diagram 3.3 control interface description the ic can be controlled either by a host using an i2c interface, or by a general purpose host interface. these interfaces provide the same functions and are described in the following sections. the selection is per- formed by the means of the pin seli2c: when high, this pin indicates that the i2c interface is used. when low, the parallel interface is used. 3.3.1 parallel control interface when the pin seli2c is low, the control of the chip is performed through the parallel interface. when accessing the device through the parallel interface, the following signals are used: - the address bus a[7..0]. it is used to select one of the 256 register locations. - the data bus data[7..0]. if a read cycle is requested, the data lines d[7:0] will be driven by the ic. for a write cycle, the STA310 will latch the data placed on the data lines when the wait signal is driven high. - the signal r/w . it defines the type of register access: either read (when high), or write (when low). some registers can be either written or read, some are read only, some are write only. - the signal dcsb . a cycle is defined by the assertion of the signal dcsb . note: 1. the address bus a[7..0], and read/write signal r/w must be setup before the dcsb line is activated. pcmout1 pcmout3 STA310 lpcm pcm sample rate converter pcmout0 pink noise gen beep tone gen l/lt r/rt c lfe ls rs prologic decoder delay delay delay l r c lfe ls rs downmix lt/rt lvcr rvcr iec958 formatter i958out down-sampling 96/48khz video spdif mode switch null data iec 1937 (ac-3 / mpeg 2) l r c lfe ls rs downmix 2 6 pcmout2 2 to 6 ch 63 60 61 62 sin2 lrclkin2 dstrb2 req2 i2s_in2 73 delay delay delay delay delay 76 77 72 63 sclk 68 lrclk 69 pcmclk 31 clk 64 clkout system and audio clocks 58 switctch pcm cdda mpeg 1 layer 1-2 2/0 2to2 6to2 voice effects: echo, chorus reverb gain level sensitive cancel mp3 6 6 2 2 2 2 switch ac-3 STA310 6 1..4 1..6 pcmmixing bass redirection / vol ctrl control 53 46 43 48 21 d[0..7] a[0..7] maini2cadr sclki2c sdai2c irq dcsb pes parser i2s_in1 pes parser frame buffer 42 41 40 37 sin lrclkin dstrb req packet formatter pts mpeg 2 mlp
9/90 STA310 - the signal wait . this signal is always driven low in response to the dcsb assertion. the timing diagrams for the parallel control interface are given in electrical specifications on page 5 . 3.4 i 2 c control interface when the pin seli2c is high, the chip is controlled through the i2c interface. the i2c unit works at up to 400khz in slave mode with 7-bit addressing. - the pin maini2cadr selects the device address. when maini2cadr is high the slave address is 0x5c, when low the device address is equal to the value on the address bus (a0...a6). - the pin sdai2c is the serial data line. - the pin sclki2c is the serial clock. the i2c bus standard does not specify sub-addressing. there are thus potentially multiple ways to implement it. any implementation that respects the standard is of course legal but a particular implementation is used by many companies. the following paragraphs describe this implementation. 3.4.1 protocol description for write accesses only, the first data which follows the slave address is always the sub-address. this is the one and only way to declare the sub-address. it should be noticed that the sub-address is implement- ed as a standard data on the i2c bus protocol point of view. it is a sub-address because the slave knows that it must load its address pointer with the first data sent by the master. see in the appendix x.x for i 2 c message format examples. 3.5 decoding process the decoding process in the STA310 is done in several stages: - parsing, - main decoding, - post decoding, - bass redirection, - volume and balance control. each of the stages can be activated or bypassed according to the configuration registers. parsing the bitstream parsing (performed by the input processor) is in charge of discarding all the non audio information in order to transmit to the next stage (the circular frame buffer) only the audio elementary stream (ac3, mpeg1/ 2, lpcm, pcm, dvd audio). the parsing stage operates in two phases: the packet parser unpacks the stream, the audio parser checks the syntax of the bitstream. main decoding the input of this stage is an elementary stream, the outputs are decoded samples. the number of output chan- nels is defined by the downmix register (1 channel up to 6 channels). for details, please refer to the description of the register. the decoding formats currently supported are ac3, mpeg1 layers i and ii, mpeg2 layer ii, lpcm. it is neces- sary to select the appropriate stream format by configuring the registers streamsel and decodesel before running the decoder.
STA310 10/90 post decoding the post decoding includes specific pcm processing: dc filter, de-emphasis filter, downsampling filter. these filters can be independently enabled or disabled through the register dwsmode. it provides also a pro logic decoder, which is described in detail in a next section. bass redirection this stage redirects the low frequency signals to the subwoofer. the subwoofer is extracted from the other channels (l, r, c, ls, rs, lfe). there are six possible configurations to extract the subwoofer channel, which can be selected thanks to the ocfg register. volume and balance control the volume is a master volume (no independent control for each channel). it is controlled by the pcmscale register, which enables to attenuate the signals by steps of 2db. two balance controls are available: one for left/right channels, one for left surround/right surround channels. they are configurable by means of registers bal_lr (left-right balance) and bal_sur (left surround-right surround balance), which provide attenuation of signals by steps of 0.5db. 4 operation 4.1 reset the STA310 can be reset either by a hardware reset or by a software reset: - the hardware reset is sent when the pin reset is activated low during at least 60ns. this is equiv- alent to a power-on reset. this resets all the configuration registers, i.e. pll registers (pllsys, pllpcm), interrupt registers (inte, int, error), interface registers (sin_setup, can_setup) and command registers (softreset, run, play, mute, skip_frame, repeat_frame). - the software reset is sent when the register softreset is written to 1 (the register is automatically reset once the software reset is performed). it resets only the interrupt related registers (inte, int, error) and the command registers (softreset, run, play, mute, skip_frame, repeat_frame). all other decoding configurations are not c hanged by softreset. some information concerning the post-processing are anywayt of date after a soft-reset note: 1. the chip must be soft reset before changing any configuration register.
11/90 STA310 4.2 clocks there are two embedded plls in the STA310: the system pll and the pcm pll. the following is the block diagram of the system and audio clocks used in the STA310 figure 3. pll block diagram figure 4. block diagram of functional pll spdif pll audio pll sys plls_config 78 rxn rxp periph 2 periph 3 / 2 / 2 / n clk clkout periph 1 w r i sclock lrclk pcmout0,1,2,3 pcmclk pcmclk_en pcm_clk sys_clk dsp core pcm_out sys_clockout vco charge pump div m+1 switching circuit div (x+1) pfd r c c3 ip uvco frac dn oclk analog part filter (external) div n+1 clkin (27mhz) pll_disable update_frac
STA310 12/90 4.2.1 system clock the system clock sent to the dsp core and the peripherals can be derived from 4 sources and the selection is performed through an host register; external clock, external clock divided by 2, internal system pll and inter- nal system pll divided by 2. the system pll is used to create the system clock from the input clock. this pll is software programmable through the host registers mechanism. the system pll is used to set the any frequency up to the maximum allowed device speed. after hard reset the system clock is running at 47.25mhz. an rc network must be con- nected to the filter pin pllsf. the system clock is output on the pin clkout after a programmable divider ranging from 1 to 16. 4.2.2 dac clocks 4.2.2.1 pcm clock the pcm clock can be either input to the device or generated by the internal pll or recovered by the embedded spdif receiver. the selection is done via the host registers. after a hardware reset, the internal pll is disabled and the pcmclk pad is an input. pcmclk may be equal to the pcm output bit rate, or it may be an integer multiple of this, allowing the use of oversampling d-a con- verters. the internal fractional pll is able to generate pcmclk at any fsx oversampling factor frequencies, where fs is any multiple or sub-multiple of the two 44.1khz and 48khz sampling frequencies. an rc network must be connected to the filter pin pllaf; refer to external circuitry on page 9 for recommended values. if the pcmclk is recovered from the embedded spdif receiver, the only supported overampling frquency is 128 fs. 4.2.2.2 bit clock sclk the pcm serial clock sclk is the bit clock. it provides clocks for each time slot (16 cycles for each channel in 16-bit mode, 32 cycles for each channel in 18-, 20-, 24-bit modes). the frequency of sclk is therefore fixed to 2 x nb time slots x fs, where fs is the sample frequency. the clock is derived from the clock pcmclk. the register pcmdivider must be configured according to the selected output precision and the frequency of pcmclk, so that the device can construct sclk: fsclk = fpcmclk / (2 x (pcmdivider+1)) gives table 1. the value of pcmdivider = 0 is reserved. if this number is loaded, the divider is bypassed and the frequency of sclk equals the frequency of pcmclk. the pcmdivider register must be setup before the output of sclk starts. this can be done by first disabling pcm outputs, by de-asserting the mute and play commands and then writing into the pcmdivider register. once the register is setup, the mute and/or play commands can be asserted. pcmdivider can not be changed on the fly. pcm divider value mode description 5 pcmclk = 384 fs, dac is 16-bit mode 3 pcmlk = 256 fs, dac is 16-bit mode 2 pcmlk = 384 fs, dac is 32-bit mode 1 pcmlk = 256 fs, dac is 32-bit mode
13/90 STA310 4.2.2.3 word clock lrclk the frequency of lrclk is given by: - flrclk = fsclk/32; for 16 bit pcm output, - flrclk = fsclk/64; for 18, 20 or 24 bits pcm output. no special configuration is required. the polarity can be changed in the register pcmconf, by setting up the field inv as needed. 4.3 decoding states there are two different decoder states: idle state and decode state (see figure 3). to change states, register figure 5. decoding states idle mode this is the state entered after a hardware or software reset. in this state, the embedded dsp does not decode, i.e. no data are processed. the chip is waiting for the run command, and during this state all configuration registers must be initialized. in this state, even if the chip is not processing data, the dacs clocks can be output, which enables to setup the external dacs. once the pcmclk, sclk and lrclk clocks are configured, it is- possible to output them by setting the mute register.i table 2. idle mode. play and mute commands effects note: 1. the play command has no effect in this state as the decoder is not running. it can however be sent and it will be taken into account as soon as the decoder enters the decode state. decode mode this state is entered after the run command has been sent (i.e. run register = 1). in this mode, the data are processed. the decoder can play sound, or mute the outputs, by using the play and mute registers: - to decode streams, the play register must be set. when decoding, the sound will be sent to outputs if the mute register is reset. the outputs are muted if the mute register is set. - to stop decoding, the play register should be reset. resuming decoding is performed by writing play to 1 again play mute clock (sclk, lrclk) state pcm output x 0 not running 0 x 1 running 0 idle mode init mode decode mode time soft reset run command decoder ready to play sample
STA310 14/90 table 3. decode mode. play and mute commands effects note: 1. it is not possible to change configuration registers in this state. it is necessary to soft reset the chip before. only the following reg- isters can be changed on-the-fly: pcm_scale, bal_lr, bal_sur, ocfg, downmix registers. 4.4 data input interface description. figure 6. block diagram of data flow play mute clock state pcm output decoding 0 0 not running 0 no 0 1 running 0 no 1 0 running decoded samples yes 1 1 running 0 yes host control host registers 256 byte i 2 s i 2 s in test interface fifo dsp core packet parser audio parser dbit/ nbit null data pcm switch frame buffer & dma spdif mode switch audio & system clocks plls iec958 formatter 8 sta120 first data input stream second data input stream host interface pcm out block iec 1937 (ac3/mpeg 2/dts) 8 3 3 3 8 r0 w r1 main_i2c_adr req req2 test smode d00au1228 sel_i2c sda_i2c scl_i2c wait dcsb rwb a0 to a7 d0 to d7 dstrb sin sin2 spdif1_a spdif1_b lrclkin lrclkin2 dstrb2 reset clk clkout pcmclk lrclk sclk pcmout0 pcmout3 pcmout2 pcmout1 spdif_o
15/90 STA310 two independent inputs are available on the STA310. the main one allows to enter input data stream through through: - a serial interface (referred to as data serial interface), - and a parallel interface (referred to as data parallel interface). the choice is performed by the register sin_setup. 4.4.1 data serial interface when the serial mode is selected, the bitstreams can be entered into the STA310 through either: - a four-signal data interface or , - trough a spdif input (no external circuit is required). the four-signal data interface (see figure 5) provides: - an input data line sin, - an input clock dstr , - a word clock input lrclkin - and a hand-shake output signal req . - note: 1. only 16-bit pcm streams are supported. for 20-bit or 24-bit pcm, the 4 or 8 least significant bits are ignored . the specifications of those signals can be configured by the means of the register can_setup. two modes exist in serial mode, one that uses the lrclkin pin and one that does not use the lrclkin pin. 4.4.1.1 modes without the lrclkin pin in this mode the signal lrclkin is not used by the STA310. the input data sin is sampled on the rising edge of dstr . when the STA310 input buffer is full the req signal is asserted. the polarity of req signal is pro- grammable through the register sin_setup. the data must be sent most significant bits first. when the decoder cannot accept further data the req is de-asserted and the dstr clock must be stopped as soon as possible to avoid data loss. after the req is de-asserted, the decoder is still able to accept data for a limited number of clock cycles. the maximum number of data that can be transmitted with respect to the change of req is given by the follow- ing formula: nbits = 23 - 6 * f dstr /33mhz, where: f dstr is the dstr clock frequency, (max is 33 mhz). 4.4.1.2 modes using the lrclkin pin when receiving data from an a/d converter or from an s/pdif receiver, the signal lrclkin is used. the lrclkin signal is used to make the distinction between the left and right channels. any edge of the lr- clkin signal indicates a word boundary. the data transfer between the input interface and the fifo is done on a byte basis. after the edge (rising or falling) of the lrclkin, a new byte is transferred to the first stage of the STA310 every 8 dstr clock cycles. if the number of time slots is not a multiple of 8, the remaining data is lost. the polarity of lrclkin and dstr is programmable. the lrclkin can be delayed by one time slot, in order to support pcm delayed mode. all these configurations are programmable through the can_setup register. the register can_setup has 4 significant bits, and each bit has a specific meaning, see can_setup on page 41 . only the first byte is transferred to the STA310 because the number of time slots is 12 (8 + 4). sin and lrclkin are sampled on the falling edge of dstr in this case sin_setup = 3 and can_setup = leftfirstchannel + fallingstrobe + allslot = 2 + 4 + 8 = 14
STA310 16/90 table 4. figure 7. example 2: only the first 2 bytes are transferred to the STA310 because the number of slots is 20 (16 + 4). sin and lrclkin are sampled on the fa lling edge of dstr. the data is in delayed mode. the register configuration is sin_setup=3 and can_setup = delaymode + leftfirstchannel + fa llingstrobe + allslot = 1 + 2 + 4 + 8 = 15. this mode is a specific mode where only the first 16 data bits are transferred. the remaining bits are discarded. the register configuration is sin_setup = 3 and can_setup = delaymode + fa llingstrobe = 1 + 4 = 5. 4.4.1.3 spdif input a true spdif input spdif (pcm audio samples) or iec-61937 (compressed data) is selectable as a main serial input. 4.4.1.4 autodetected formats the STA310 cut 2.0 is able the following audio format changes on the s/pdif input table 5. audio format detection when set when clear name bit 0 the input data is one slot delayed with respect to lrclkin the input data is not delayed delaymode bit 1 first channel when lrclkin is set first channel when lrclkin is reset leftfirstchannel bit 2 data are sampled on falling edge of dstr data are sampled on rising edge of dstr fallingstrobe bit 3 all the bytes are extracted only the first 16 data bits are extracted allslot before after ac3 pcm ac3 mpeg mpeg ac3 mpeg pcm pcm ac3 pcm mpeg bit 0 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 7 bit 4 bit 5 bit 6 bit 0 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 7 bit 4 bit 5 bit 6 lrclkin dstr sin transferred data discarded data
17/90 STA310 4.4.1.5 second input a second independent input allows to input bitstreams in serial mode. this second input can be used, to input audio stream from a microphone, while we decode a data stream trough the main input. 4.4.2 data parallel interface two ways are available to input data in parallel mode: - either through the parallel data bus, shared with the external controller, - or through the datain register 4.4.2.1 using the parallel data bus in this mode the data must be presented on the 8-bit parallel host data bus d[7..0]. note that this bus is shared with the external controller. on the rising clock of dstr the data byte is sampled by the STA310. the signal req is used to signal when the input fifo is full. when req is de-asserted the transfer must be stopped to avoid data loss. after the req is de-asserted, the decoder is st ill able to accept data for a limited number of clock cycles. the maximum number of data that can be transmitted with respect to the change of req is given by the follow- ing formula: nbits = 23 - 6 * f dstr /33mhz, where: f dstr is the dstr clock frequency, (max is 33 mhz). the signals dstr and dcsb are used to make the distinction between stream data (strobed by dstr ) and control data (strobed by dcsb ). to avoid conflicts, the dstr signal and the dcsb signal must respect given timing constraints. 4.4.2.2 using the datain register the data can be input by using the control parallel interface as if accessing any other register. the signal dcsb is therefore used. when using this register to input data stream, there is no need to byte-align the data. figure 8. bit 0 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 7 bit 4 bit 5 bit 6 bit 0 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 7 bit 4 bit 5 bit 6 bit 0 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 4 bit 0 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 7 lrclkin dstr sin transferred data discarded data
STA310 18/90 figure 9. 4.5 streams parsers the parsing stage is operated by two parts: the packet parser and the audio parser. the packet parser unpacks stream, sorts packets and transmit data to the audio parser. the audio parser ver- ifies the stream syntax, extracts non-audio data and sends audio data to the frame buffer. packet parser before unpacking packets and transmitting data, the packet parser needs to detect the packet start by recog- nizing the packet synchronization word. it is possible to force the parser to search for two packet synchronization words before starting to unpack and transmit. this is done by setting the register packet_lock to 1. otherwise, the packet parser w ill start handling the stream once it has detected information matching the packet synchronization word. the packet parser is also able to perform selective decoding: it can decode audio packets that are matching a specified id. this id is specified in audio_id and audio_id_ext registers, and the function is enabled by set- ting the audio_id_en register. audio parser the audio parser needs to detect the audio synchronization word corresponding to the type of stream that must be decoded. it is possible to force the audio parser to detect more than one synchronization word before pars- ing. this is done by setting the sync_lock register to a value between 1 and 3 - number of supplementary sync words to detect before considering to be synchronized. the status of synchronization of both parsers is provided in the register sync_status. each time the syn- chronization status of one of the two parsers changes, the interrupt syn is generated (if enabled) and the status can be read in sync_status. 4.6 decoding modes 4.6.1 ac-3 the STA310 is dolby digital certified for class a products. the decoder must be programmed so to specify the stream format as ac-3 encoded: register decodesel = 0. in the sections below are provided the modes specific to the ac-3 decoding. 4.6.1.1 compression modes four compression modes are provided in the STA310: bit 0 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 7 bit 4 bit 5 bit 6 bit 4 bit 5 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 7 bit 0 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 4 bit 4 bit 5 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 lrclkin dstr sin transferred data discarded data
19/90 STA310 - custom a (also named custom 0 in dolby specifications), - custom d (also named custom 1 in dolby specifications), - line mode, - rf mode. these modes refer to different implementation of the dialog normalization and dynamic range control features. the mode is selected by programming the register comp_mod to the appropriate value. line mode in line mode (comp_mod = 2), the dialog normalization is always enabled. it is done by the decoder itself and the dialog is reproduced at a constant level. the dynamic range control variable encoded in the bitstream is used and can be scaled by the two scaling reg- isters hdr (for high-level cut compression) and ldr (for low-level boost compression). in case of 2/0 downmix, the high-level cut compression is not scalable. rf mode in rf mode (comp_mod=3), the dialog normalization is always performed by the decoder. the dialog is re- produced at a constant level. the dynamic range control and heavy compression variables encoded in the bitstream are used, but the com- pression scaling is not allowed. this means that the hdr and ldr registers can not be used in this mode. a +11db gain shift is applied on the output channels. custom a mode in custom a mode (comp_mod=0), the dialog normalization is not performed by the decoder and must be done by another circuit externally. the dynamic range control variable encoded in the bitstream is used and can be scaled by the two scaling reg- isters hdr (for high-level cut compression) and ldr (for low-level boost compression). custom d mode in custom d mode (comp_mod=1), the dialog normalization is performed by the decoder. the dynamic range control variable encoded in the bitstream is used and can be scaled by the two scaling registers hdr (for high- level cut compression) and ldr (for low-level boost compression). 4.6.1.2 karaoke mode the ac-3 decoder is karaoke aware and capable. a karaoke bitstream can be composed of 5 channels: l for left, r for right, m for guide melody, v1 for vocal track 1 and v2 for vocal track 2. - when in karaoke aware mode, the channels l,r and m are reproduced, and the channels v1 and v2 are reproduced at a level fixed by the bitstream. - when in karaoke capable mode, it is possible to choose to reproduce one, two or none of the two incoming vocal tracks, v1 and v2. the karaoke decoder is activated by the use of karamode register, which specifies the downmix for the dif- ferent modes. this register replaces downmix register. it is however possible to consider the incoming karaoke channels as any other multichannel stream and output it with a downmix specified in downmix reg- ister. for details, refer to the digital audio compression ac-3 atsc standard, annex c.
STA310 20/90 4.6.1.3 dual mode the dual mode corresponds to a mode where two completely independent mono program channels (e.g. bilin- gual) are encoded in the bitstream, referenced to as channel 1 and channel 2. the possible ways to output channels on left/right outputs are: - output channel 1 on both l/r outputs, - output channel 2 on both l/r outputs, - mix channels 1 and 2 to monophonic and output on both l/r, - output channel 1 on left output, and channel 2 on right output. this channels downmix is specified in the register dualmode. 4.6.2 mpeg the STA310 is able to decode mpeg-1 layeri and layerii encoded data, as well as mpeg-2 layer i, layer ii data without extension (i.e. 2-channel streams). the mpeg input format should be specified in the decodesel register: - decodesel=1 for mpeg1. the mc bit in mc_off register should be set. - decodesel=2 for mpeg2. the mc bit in mc_off register should be set. 4.6.3 mp3 the STA310 is able to decoder mpeg2 layer iii (mp3) data. the mp3 input format aboved be specified in the decodesel register: - decodesel=9 for mp3. 4.6.3.1 dual mode the dual mode corresponds to a mode where two completely independent mono program channels (e.g. bilin- gual) are encoded in the 2-channel incoming bitstream, referenced to as channel 1 and channel 2. the audio decoder allows to: - output channel 1 on both l/r outputs, - output channel 2 on both l/r outputs, - mix channels 1 and 2 to monophonic and output on both l/r, - output channel 1 on left output, and channel 2 on right output. the output configuration is chosen by special downmix for dual mode through register mpeg_dual.
21/90 STA310 4.6.3.2 decoding flow figure 10. ac-3 decoding flow figure 11. mpeg decoding flow 4.6.4 pcm/lpcm the decoder supports pcm (2-channels) and lpcm video (8-channels) and audio (6-channels) streams. this is selected by decodesel=3. 4.6.4.1 downsampling filter when decoding pcm/lpcm streams encoded at 96khz, it is possible to use a filter that downsamples the stream from 96khz to 48khz. the chip can not output streams at 96khz. the register dwsmode is used to configure the use of this filter. figure 12. pcm/lpcm decoding flow data input interface fifo 256 bytes packet parser frame parser frame buffer ac-3 decoder downmix bass redirection volume, balance l r c lfe ls rs pcm_out pcm_out pcm_out 6-channel ac-3 data l r c lfe ls rs l r c sub ls rs l r c sub ls rs delay delay delay delay delay delay data input interface fifo 256 bytes packet parser frame parser frame buffer 2-channel mpeg1/2 data mpeg1/2 decoder l r downmix volume, balance l r delay delay pcm_out pcm_out pcm_out zeros l r bass redirection l r sub sub delay zeros data input interface fifo 256 bytes packet parser frame parser frame buffer 2-channel pcm/lpcm data downsampling filter 96khz -> 48khz l r volume, bal ance l r delay delay pcm_out0 pcm_out1 pcm_out2 zeros bass redirection l r sub sub delay zeros
STA310 22/90 4.6.5 mlp mlp is a lossless coding system for use on digital audio data originally represented as linear pcm. mlp is man- datory in dvd audio. it allows transmission and storage of up to 6 channels. each up to 24 bits precision and with sample rates between 44.1 khz and 192khz. - decodesel = 8 4.6.6 cdda - decodesel = 5 4.6.7 beep tone - decodesel = 7 4.6.8 pink noise generator the pink noise generator can be used to position the speakers in the listening room so to benefit of the best listening conditions. the decoder must be programmed so to generate pink noise by writing 4 in the decodesel register. the downmix register is used to select independently the channels on which the pink noise will be output. when generating pink noise, the output configuration should be: ocfg=0 and pcm_scale=0. figure 13. pink noise generator flow 4.7 post processing the following post processing alghorithms are available 4.7.1 prologic pro logic compatible downmix the STA310 can decode an ac-3 multichannel bitstream and encode it to provide a 2-channel pro logic com- patible output (lt, rt). these 2 channels are the result of a specific downmix referred to as pro logic compatible. this downmix is selected by the register downmix. the 2 channels can be used as the input of a pro logic decoder and player (e.g. home theatre). pro logic decoding the STA310 can decode a 2-channel pro logic bitstream. the 2 channels could come from a cd player, an ac-3 2-channel bitstream or an mpeg1 bitstream. the 2-channel bitstream can be converted into a 4-channel output (l, r, c, s). the surround (s) is simultaneously sent on ls and rs channels. a pro logic downmix en- pink pink noise generator noise downmix l r c lfe ls rs pcm_out0 pcm_out1 pcm_out2 no bass redirection: ocfg = 0 l r c lfe ls rs
23/90 STA310 ables to configure which channels to output on pcm data. this is done through the register pl_dwn. an auto-balance feature is available and activated through pl_ab register. the delay on surround channel is configurable thanks to the lsdly register (while resetting the rsdly register). the bass redirection is performed after the pro logic decode. the same bass redirection configuration than those available in non-pro logic modes can be used except that the surround channels will not be added to the bass redirection. in the case of ac-3 or mpeg the STA310 is therefore capable of first decoding the ac-3 or mpeg stream then performing the pro logic decode. 4.7.2 others - karaoke system - bass management + volume control -deemphasis - dc remove 4.8 how to choose a decoder to set up the device you have to select two registers. the first one is decodesel for audio data type, the second one is streamsel for transport data type, the streamsel can be set-up as follows: 0= pes 1= pes dvd video 2= packet mpeg1 3= elementary stream or iec.60958 4= reserved 5= iec.61937 6= pes dvd audio so the possible configurations on listed in the following table: table 6. possible configurations: streamsel decodesel mode 0 0 mpeg2 pes carrying dolby digital (atsc) 0 1 mpeg2 pes carrying mpeg1 frames 0 2 mpeg2 pes carrying mpeg2 frames 1 0 mpeg2 pes carrying dolby digital frames for dvd video 1 2 mpeg2 pes carrying mpeg2 frames for dvd video 1 3 mpeg2 pes carrying linear pcm frames for dvd video 1 1 mpeg1 packet carrying mpeg1 frames 3 0 dolby digital frame elementary streams 3 1 mpeg1 frame elementary streams 3 2 mpeg2 frame elementary streams 3 3 stereo pcm (16bits samples) 3 4 pink noise generator
STA310 24/90 4.9 how to program a post processing 4.9.1 2 registers for the mode: pdec (0x62) to define the type of postprocessing 4.9.2 1 or 2 registers to control the postprocessing prologic decoder (pdec = 0x01): remark: when playing dolby digital prologic encoded, if pl_downmix is correctly set, prologic decoder is automatically applied even if the register pdec different to 1. 3 5 cdda frames 3 7 beep tone generator 3 9 mp3 frame elementary streams 5 0 iec61937 input with dolby digital frames 5 1 iec61937 input with mpeg1 frames 5 2 iec61937 input with mpeg2 frames 6 3 mpeg2 pes carrying linear pcm for dvd audio 6 8 mpeg2 pes carrying mpl for dvd audio pdec mode 0x01 prologic 0x02 mpeg 1/2 dynamic range 0x08 double stereo 0x10 dc remove 0x20 deemphasis filter pl abl ws (0x64) effect 1 autobalance 2 widesurround pl downmix (0x65) prologic downmix 0,1,2 prologic not applied 3 3/0 (l, r, c) 4 2/1 (l, r, ls) phantom 5 3/1 (l, r, ls) 6 2/2 (l, r, ls, rs) phantom 7 3/2 (l, c, r, ls, rs) streamsel decodesel mode
25/90 STA310 4.10 what can be processed at the same time same time 1 same time 2 5 pcm output configurations 5.1 output configurations the figure below shows the different configurations supported at pcm output stage. they are selected by the ocfg register contents. - in configuration 1, 3 and 4, the main channels are attenuated by 18.5db, and the lfe by 8.5db before summing. after digital/analog conversion, the subwoofer preamplifier has to compensate for the different gains of the main channels and subwoofer. - in configuration 2, the main channels are attenuated by 16db and the lfe by 6db before processing. - in configuration 0, outputs are only scaled and rounded (see next section). the same configurations will be used in case of a decoded pro logic program with the exception that the sur- round channels w ill not be added to the bass redirection (the surround channels of a pro logic program are band limited and bass is considered as leakage). decoder mpeg1 mp3 ac3 mpeg2 lpcm video pcm mlp lpcm audio pink noise beep tone post pcrocessing bass management commands mute skip frame pause pause block volume control s/ pdif output pcm ( left ,righ t pcm (vcrs) encoded mute off post pcrocessing prologic post pcrocessing karaoke channel delay post pcrocessing karaoke channel delay post pcrocessing karaoke channel delay
STA310 26/90 figure 14. pcm output configurations 5.2 pcm scaling pcm scaling is needed for every decoding mode (ac3, pro logic, mpeg, pcm). it is applied at the end of the filtering steps before pcm output, allowing maximum effective word width for most of the signal processing be- fore. master volume (pcm_scale register) and balances (bal_lr and bal_sur registers) are implemented for pcm scaling. 5.3 output quantization for optimal results for 16/18/20-bit dacs, a quantization with rounding is applied together with the pcm scaling. the sample value is multiplied by a rounding factor and rounded to 24 bits. the result is then left shifted (4/6/8) for pcm output. the output precision is selectable from the 16bits/word to 24 bits/word by configuring the field prec in the reg- ister pcmconf. 5.4 interface and output formats the decoded audio data are output in serial pcm format. the interface consists of the following signals pcm_out0, 1, 2 pcm data, output, sclk bit clock (or serial clock), output, lrclk word clock (or left/right channel select clock), output, pcmclk pcm clock, input or output (see clocks on page 11 for details). ls ls ll cc rr ls ls configuration 0 ll cc rr ls ls rs rs not used with prologic -18.5db not used in configuration 4 -8,5db lfe sub configuration 1 configurations 3 and 4 configuration 2 not used with prologic ll cc rr ls ls rs rs lfe sub -8,5db -18.5db rs rs lfe lfe ll not used with prologic -16db cc -16db -16db rs rs -16db lfe -6db -4db rr -16db
27/90 STA310 5.4.1 output precision and format selection output precision is selectable from 16 bits/word to 24 bits/word by setting the output precision select, in the pc- mconf (16-, 18-, 20- and 24-bit mode) register. in 16-bit mode, data may be output either with the most significant bit first or least significant bit first. this is configured by the contents of the field ord in the pcmconf register. when pcmconf.prec is more than 16 bits, 32 bits are output for each channel. in this configuration, the field for of register pcmconf is used to select sony or i2s- compatible format. the field dif of pcmconf is used to position the 18, 20 or 24 bits either at the beginning or at the end of each 32-bit frame. figure 15. output formats m conf.pec pcm conf.ord pcm conf.for pcm conf.dif data in sample memory data [23:0] data sent on the pcm serial output (left bit first) 0:16-bit mode 1 na na {d23-d8}-{8*0} {d8-d23}: 16 bits 0:16-bit mode 0 na na {d23-d8}-{8*0} {d23-d8}: 16 bits 1:18-bit mode na 0 0 {d23-d6}-{6*0} {13*0}{0}{d23-d6}: 32 bits 1:18-bit mode na 0 1 {d23-d6}-{6*0} {0}{d23-d6}{13*0}: 32 bits 1:18-bit mode na 1 0 {d23-d6}-{6*0} {14*d23}{d26*d6}: 32 bits 1:18-bit mode na 1 1 {d23-d6}-{6*0} {d23-d6}{14*0}: 32 bits 2:20-bit mode na 0 0 {d23-d4}-{4*0} {11*0}{0}{d23-d4}: 32 bits 2:20-bit mode na 0 1 {d23-d4}-{4*0} {0}{d23-d4}{11*0}: 32 bits 2:20-bit mode na 1 0 {d23-d4}-{4*0} {12*d23}{d23-d4}: 32 bits 2:20-bit mode na 1 1 {d23-d4}-{4*0} {d23-d4}{12*0}: 32 bits 3:24-bit mode na 0 0 {d23-d0} {6*0}{0}{d23-d0}: 32 bits 3:24-bit mode na 0 1 {d23-d0} {0}{d23-d0}{7*0}: 32 bits 3:24-bit mode na 1 0 {d23-d0} {8*d23}{d23-d0}: 32 bits 3:24-bit mode na 1 1 {d23-d0} {d23-d0}{8*0}: 32 bits lrclk pcm_out[2:0] pcm_out[2:0] lrclk pcm_out[2:0] pcm_out[2:0] pcm_out[2:0] pcm_out[2:0] 16 sclk cycles 16 sclk cycles 32 sclk cycles 32 sclk cycles m s l s m s l s l s m s l s m s pcmconf.ord = 0, pcmconf.prec is 16 bits mode pcmconf.ord = 1, pcmconf.prec is 16 bits mode m s l s m s l s 00 m s l s m s l s 0 0 00 00 m s l s m s l s m s l s m s l s 18, 20 or 24 bits 18, 20 or 24 bits 18, 20 or 24 bits 18, 20 or 24 bits 18, 20 or 24 bits 18, 20 or 24 bits 18, 20 or 24 bits 18, 20 or 24 bits msb msb pcmconf.for = 1 pcmconf.dif = 1 pcmconf.for = 0 pcmconf.dif = 0 pcmconf.for = 0 pcmconf.dif = 1 pcmconf.for = 1 pcmconf.dif = 0
STA310 28/90 how to read the above table: the first 4 columns list the possible configurations for output formats on the pcm outputs. the 5th column gives the description of the internal 24-bit decoded, scaled and rounded audio samples as they are stored in memory. these 24 bits are referred to as d23, d22,..., d0, where msb=d23, lsb=d0. the last column describes the se- quence of bits that are output on pcm_out according to the selected format. example 1: in 16-bit mode, with pcmconf.ord=1: in memory, 24 bits are stored, where only the 16 msb bits (d23, d22,... to d8) are significant and the 8 remaining bits are 0. this is noted: {d23-d8} {8*0}. the data are sent lsb first, i.e. d8 is sent first and d23 is sent last. this is noted {d8-d23}. 16 bits only are transmitted per channel. example 2: in 20-bit mode (pcmconf.ord field is meaningless in this mode), with pcmconf.for=1 and pcmconf.dif=0: in memory, 24 bits are stored, where only the 20 msb (d23 to d4) are significant and the remaining 4 lsb are 0.this is noted: {d23-d4} {4*0}. 32 bits are transmitted per channel on the pcm outputs: the 12 first transmitted bits are d23, the last bits are d23 to d4, where d23 is transmitted first. this is noted: {12*d23} {d23-d4}. 5.4.2 clocks polarity selection the polarity of the pcm serial output clock, sclk and the polarity of the pcm word clock lrclk are selected by the field scl and inv respectively, in the pcmconf register. 5.4.3 i 2 s format compatible outputs to output i2s compatible data, the pcmconf register must be configured as follows 5.4.4 sony format compatible outputs figure 16. sclk polarity figure 17. lrclk polarit y pcmconf.dif = 1 not right padded, pcmconf.for = 0 i2s format, pcmconf.inv = 0 do not invert lrclk, pcmconf.scl = 0 do not invert sclk. pcmconf.for = 1 sony format, pcmconf.inv = 1 invert lrclk. sclk lrclk pcm_out0, 1, 2 scl = 0 sclk lrclk pcm_out0, 1, 2 scl = 1 lrclk left right left right inv = 1 inv = 0
29/90 STA310 6 s/pdif output the s/pdif output pad is a ttl output pad with slew rate control. the output dc capability is 4 ma. the voltage drop is 3v. this output must be connected to a ttl driver before the transformer. the s/pdif output supports spdif and iec-61937 standards. several registers must be initialized to configure the spdif output: - the category code must be entered in the iec958_cat register. it is related to the type of application. the category code is specified in the digital output interface standard. - the status bits that will be transmitted on the spdif output, must be programmed in the iec958_status register. - iec clock setting must be specified in the iec958_conf register. - the data type dependent information can be specified in the iec958_dtdi register. - the s/pdif type is selected through the iec958_cmd register: the iec unit can output decoded data (pcm mode), encoded data, or null data. note: 1. the spdif output handles only 48khz or 44.1khz sample rates. 6.1 spdif output when configured in spdif mode, the s/pdif output is used to transmit either the l/r channels (pcmout1) or vcr_l/vcr_r (pcmout0). the selection is done by choosing the pcm mode and aux = 1 in the register spdif_cmd and resetting the com status of spdif_status register. 6.2 iec-61937 output when configured in iec-61937 mode, the s/pdif output is used to transmit encoded data taken directly from the frame buffer. the selection is done by choosing the encoded mode (enc mode) in the register iec958_cmd and setting the bit com in iec958_status register. the decompressed data are output simultaneously on the pcm_out outputs. latency in software versions 6 and later for software versions 6 and later, when choosing to output encoded s/pdif data, a latency is automatically in- serted between s/pdif output and pcm outputs. the pcm outputs are delayed compared to the spdif output. the latency value is defined by standards and applied when the auto-latency mode is selected. ac3 decoding mpeg decoding where fs is the sampling frequency in khz, framesize is expressed in 16-bit words, datarate is the bit rate in kbits per second. the latency insertion can not be disabled however it can be programmed to values different from those required in the standard by selecting the user-programmable-latency mode (by setting the bit 7 of iec858_conf regis- latency = 1/fs * (1/3 * framesize + 256) = 1/fs * (32 * datarate/fs + 256) latency = 1/fs * (36 * datarate/fs + 96)
STA310 30/90 ter). in this case, the latency is specified in the iec958_latency register. note that there are minimum and maximum values to respect table 7. if those limits are not respected, an error interrupt occurs corresponding to error type: latency_too_big, which automatically makes the chip switch to auto_latency mode. for software versions prior to 6, the latency is not implemented. 6.3 pcm null data when configured in muted mode (in the iec958_cmd register), the outputs are pcm null data. this can be used to synchronize the external iec receiver. 7 interrupts 7.1 interrupt register the decoder can signal to the external controller that an interrupt has occurred during the execution. the register inte enables to select which interrupts will be generated and output on the irq output pin. when an interrupt occurs, the signal irq is activated low and the controller can check which interrupt was de- tected by reading the register int. according to the type of interrupt detected, other information can be obtained by reading associated registers (such as stream header, type of error detected, pts value). 7.2 irq signal this signal, irq , is a three-state line. this signal indicates (by going low) when an interrupt occurs. it returns to high level once the corresponding bit in the interrupt register has been cleared. 7.3 error concealment errors are signaled as interrupts by the audio core. the error list is provided in. most of the errors are automat- ically handled by the core, some require that software be changed. ac-3 decoding errors: those errors are signaled in the error register but handled directly by the core. nothing can be done by the software. they signal that something wrong happened during the decoding. the core soft mutes the frame and continues to decode. mpeg decoding errors: those errors are also signaled in the error register but handled directly by the core. nothing can be done by the software. they signal that something wrong happened during the decoding. the core soft mutes the frame and continues to decode. only one error in this category indicates a programming error: if triggering the ac-3 mpeg min. latency max. latency min. latency max. latency 256 samples / fs 1536 samples / fs 96 samples / fs 1152 samples / fs
31/90 STA310 mpeg_ext_crc_error, the bit mc_off must be set. this indicates that the decoder tries to decode more than 2 channels whereas the incoming stream contains only 2 channels. packet and audio synchronization errors: those errors are handled internally, and usually indicate that the incoming bitstream is incorrect or incorrectly input to the chip. in those cases, the decoder resets the corresponding parsing stage (packet or audio parser) then searches for the next correct frame. miscellaneous errors: - latency_too_big error indicates a problem of latency programming which is superior to the max- imum authorized value. change the latency value or switch to auto-latency mode to solve the problem. other miscellaneous errors are internally handled.
STA310 32/90 8 audio/video synchronization 8.1 presentation time stamp detection 8.1.0.1 pts signal this signal, pts , is used to signal the detection of a presentation time stamp in a stream, for audio/video syn- chronization. when a pts is detected, the signal pts goes low during one lrclk period. it is generated while the pcm are output, so to enable the use of an external counter to synchronize the STA310 with a video decod- er. the signal is activated, even if pts interrupt is not enabled. 8.1.1 pts interrupt when enabled through the inte register, the interrupt pts is generated when a pts is detected. the interrupt is signalled on the irq output, which goes low. the irq signal is de-activated once the pts bit has been cleared in int register by reading the pts most significant bit. 8.1.2 pts interrupt and signal relative timings the irq configured as pts interrupt is output before the pts signal. the pts signal is activated at last one period of lrclk after the irq signal. 8.2 frames skip capability when the audio decoder is late compared to the video decoder, the decoder is able to skip frames. writing 1 in the skip_frame register makes the decoder ignore the next incoming frame. once skipping the frame, it con- tinues to decode the stream, and the skip_frame register is automatically reset. 8.3 frames repeat capability when the audio decoder is ahead of the video decoder, the decoder can repeat frames. writing 1 in the repeat_frame register makes the decoder repeat the current frame. once repeating the frame, the chip plays the next incoming frame, and the repeat_frame register is reset. 9 register manual 9.1 introduction the STA310 device contains 256 registers. two types of registers exist: - from address 0x00 to 0x3f, the registers are real registers that can be initialized after reset. - from address 0x40 to 0x100, they are memory locations. this means that the registers located at the address 0x40 to 0x100 can have different meanings and usage according to the mode in which the device operates. be careful that they can not be hardware reset: they contain undefined values at reset and require to be initialized after each hardware reset. in this document, only the user registers are described. the undocumented registers are reserved. these registers must never be accessed (neither in read nor in write mode). the read only registers must never be written
33/90 STA310 9.2 register map by function the following tables list the register map by address and function, then each audio decoder register is described individually table 8. code description (a) register modification is always taken into account by the audio decoder. any change to these registers is taken into account immediately. (b) register modification is taken into account after every decoded data block or just after reset (soft or hard). the decoded block is related to the granularity of the computation in the audio decoder software. a block is 256 samples in dolby digital, 96 samples in mpeg, 80 samples in lpcm/pcm. (f) register modification is taken into account after every data frame. a frame is: 1152 samples in mpeg i/ii, 1536 samples in dolby digital, 384 samples in mpeg-1 layer 1, 80 samples in lpcm/pcm. (r) register modification is taken into account only when the dsp is run after reset (soft or hard). (1) the delay registers are updated when bit 0 of the update register is set to 1. (2) the volume is updated when chan_idx is set to the appropriate value. (3) the karaoke mode is updated when kar_update is set to 1. register function hex dec name version 0x00 0 version 0x01 1 ident 0x71 113 softver setup + inputs 0x0c 12 sin_setup (a) 0x0d 13 can_setup (a) pcm configuration 0x54 84 pcmdivider (b) 0x55 85 pcmconf (b) 0x56 86 pcmcross (b) dac and pll configuration 0x05 5 sfreq (f) 0x12 18 pllctrl (f) 0x18 24 pllmask (a) 0x0e 14 data in 0x12 18 pllctrl (f) 0x11 17 pll_data (a) 0x1d 29 pll_cmd (f) 0x12 18 pll_add (f) 0xb5 181 ena_all fracpll 0xb6 182 au_pll_fracl_192 0xb7 183 au_pll_frach_192 0xb8 184 au_pll_xdiv_192 0xb9 185 au_pll_mdiv_192 0xba 186 au_pll_ndiv_192 0xbb 187 au_pll_fracl_176 0xbc 188 au_pll_frach_176 0xbd 189 au_pll_xdiv_176 0xbe 190 au_pll_mdiv_176
STA310 34/90 channel delay setup 0x57 87 ldly (1) 0x58 88 rdly (1) 0x59 89 cdly (1) 0x5a 90 subdly (1) 0x5b 91 lsdly (1) 0x5c 92 rsdly (1) 0x5d 93 update (f) 0xaf 91 lvdly (1) 0xb0 92 rvdly (1) spdif output setup 0x5e 94 spdif_cmd (r) 0x5f 95 spdif_cat (f) 0x60 96 spdif_conf (b) 0x61 97 spdif_status (b) 0x75 117 spdif_rep_time (b) 0x7e 126 spdif_latency (f) 0x7f 127 spdif_dtdi (f) command 0x10 16 softreset (a) 0x13 19 play (a) 0x14 20 mute (a) 0x72 114 run (a) 0x73 115 skip_mute_cmd (f) 0x74 116 skip_mute_value (f) interrupt 0x07, 08 7, 8 inte (a) 0x09, 0a 9, 10 int (a) interrupt status 0x40 64 sync_status 0x41 65 anccount 0x42 66 head4 (f) 0x43 67 head3 (f) 0x44, 45 68, 69 headlen (f) 0x46 - 4a 70 pts (f) 0x0f 15 error decoding algorithm 0x4c 76 streamsel (r) 0x4d 77 decodsel (r) system synchronization 0x4f 79 packet_lock (r) 0x50 80 id_en (a) 0x51 81 id (a) 0x52 82 id_ext (a) 0x53 83 sync_lock (r) post decoding and pro logic 0x62 98 pdec1 (b) 0xb1 177 pdec2 0x64 100 pl_ab (b) 0x65 101 pl_dwnx (b) 0x66 102 ocfg 0x70 112 dwsmode (b) register function hex dec name
35/90 STA310 bass redirection 0x4e 78 volume0 (2) 0x63 100 volume1 (2) 0x66 102 ocfg (b) 0x67 103 chan_idx (b) dolby digital configuration 0x68 104 ac3_decode_lfe (b) 0x69 105 ac3_comp_mod (b) 0x6a 106 ac3_hdr (b) 0x6b 107 ac3_ldr (b) 0x6c 108 ac3_rpc (b) 0x6d 109 ac3_karamode (b) 0x6e 110 ac3_dualmode (b) 0x6f 111 ac3_downmix (b) 0x76 118 ac3_status0 (f) 0x77 119 ac3_status1 (f) 0x78 120 ac3_status2 (f) 0x79 121 ac3_status3 (f) 0x7a 122 ac3_status4 (f) 0x7b 123 ac3_status5 (f) 0x7c 124 ac3_status6 (f) 0x7d 125 ac3_status7 (f) mpeg configuration 0x68 104 mp_skip_lfe (b) 0x69 105 mp_prog_number (b) 0x6e 106 mp_dualmode (b) 0x6a 110 mp_drc (b) 0x6c 108 mp_crc_off (b) 0x6d 109 mp_mc_off (b) 0x6f 111 mp_downmix (b) 0x76 118 mp_status0 (f) 0x77 119 mp_status1 (f) 0x78 120 mp_status2 (f) 0x79 121 mp_status3 (f) 0x7a 122 mp_status4 (f) 0x7b 123 mp_status5 (f) pink noise generation registers 0x6f 111 pn_downmix pcm beep-tone configuration 0x68 104 pcm_btone (b) register function hex dec name
STA310 36/90 karaoke 0x81 129 kar_mch0vol (3) 0x82 130 kar_mch1vol (3) 0x83 131 kar_keycont (3) 0x84 132 kar_keyvalue (3) 0x85 133 kar_vcancel (3) 0x86 134 kar_vvalue (3) 0x87 135 kar_mmute (3) 0x88 136 kar_vch0vol (3) 0x89 137 kar_vch1vol (3) 0x8a 138 kar_duet (3) 0x8b 139 kar_duetthresh (3) 0x8c 140 kar_voice (3) 0x8d 141 kar_vdelay (3) 0x8e 142 kar_vbal (3) 0x8f 143 kar_vmute (3) 0x90 144 kar_play (3) 0x91 145 kar_mode (3) 0x92 146 kar_din_ctl (3) 0x93 147 kar_update second serial input 0x94 148 sfreq2 0x95 149 caninput_mode linear pcm (dvd audio) registers 0x6f 111 lpcma_downmix 0x70 112 lpcma_force_dws 0x76 118 lpcma_status0 0x77 119 lpcma_status1 0x78 120 lpcma_status2 0x79 121 lpcma_status3 0x7a 122 lpcma_status4 0x7b 123 lpcma_status5 0x97 151 lpcma_dm_coeft_0 0x98 152 lpcma_dm_coeft_1 0x99 153 lpcma_dm_coeft_2 0x9a 154 lpcma_dm_coeft_3 0x9b 155 lpcma_dm_coeft_4 0x9c 156 lpcma_dm_coeft_5 0x9d 157 lpcma_dm_coeft_6 0x9e 158 lpcma_dm_coeft_7 0x9f 159 lpcma_dm_coeft_8 0xa0 160 lpcma_dm_coeft_9 0xa1 161 lpcma_dm_coeft_10 0xa2 162 lpcma_dm_coeft_11 0xa3 163 lpcma_dm_coeft_12 0xa4 164 lpcma_dm_coeft_13 linear pcm (dvd vid & pcm) registers 0x6f 111 lpcmv_downmix register function hex dec name
37/90 STA310 0x70 112 lpcmv_force_dws 0x76 118 lpcmv_status0 0x77 119 lpcmv_status1 0x78 120 lpcmv_status2 0x97 151 lpcmv_dm_coeft_0 0x98 152 lpcmv_dm_coeft_1 0x99 153 lpcmv_dm_coeft_2 0x9a 154 lpcmv_dm_coeft_3 0x9b 155 lpcmv_dm_coeft_4 0x9c 156 lpcmv_dm_coeft_5 0x9d 157 lpcmv_dm_coeft_6 0x9e 158 lpcmv_dm_coeft_7 0x9f 159 lpcmv_dm_coeft_8 0xa0 160 lpcmv_dm_coeft_9 0xa1 161 lpcmv_dm_coeft_10 0xa2 162 lpcmv_dm_coeft_11 0xa3 163 lpcmv_dm_coeft_12 0xa4 164 lpcmv_dm_coeft_13 0xa8 168 lpcmv_ch_assign 0xa9 169 lpcmv_multi_chs de-emphasis register 0xb5 181 deemph auxilliary outputs registers 0xae 174 vcr_mix 0xaf 175 vcr_ldly 0xb0 176 vcr_rdly miscellaneous 0x2b 43 breakpoint 0x3a 58 clockcmd 0xff 255 init_ram spdif autodetection 0xe0 224 autodetect_ena 0xe1 225 autodetect_sens 0xe2 226 autodetect_align register function hex dec name
STA310 38/90 9.3 version registers ident identify address: 0x01 type: ro software reset: 0x31 hardware reset: 0x31 description: ident is a read-only register and is used to identify the ic on an application board. ident always has the value 0x31. softver software version address: 0x71 type: r/w software reset: nc hardware reset: und description: this softver register is the version of the code which is running on the device. this regiter is updated by the embedded software just after a soft reset of the device: - for STA310 cut 1.0 the register contain the value 0x0a - for STA310 cut 2.0 the register contain the value 0x14 loading a patch into the STA310 w ill automatically c hange the register content. please contact st to have the correct value according to the patch being used. this register must be readonly after the STA310 has finished booting, in order to get a correct value (when init_ram register hold the value 1) version version address: 0x00 type: ro 76543210 10101100 76543210 76543210 00010000
39/90 STA310 software reset: na hardware reset: na description: this version register is read only and is used to iden- tify the audio hardware version. the version register holds a number which refers to the cut number. the version numbers are defined as below: - STA310 cut 1.0, version number is : 0x10 - STA310 cut 2.0, version number is : 0x10 9.4 setup & input registers the STA310 can get receive an input bitstream either from the i2s input or ffrom the spdif input, the selec- tion and the configuration is done through 2 registers sin_setup @ 12 and can_setup @ 13. sin setup input data setup address: 0x0c type: r/w software reset: nc hardware reset: 0 description: this register is used to configure the input data inter- face. the register must be setup before sending data to the ic. the mapping of the register isescribed be- low. remember that the data must be sent to the de- vice msb first. - spdif data frpm spdif when set to 1, data from main i 2 s input. - pol polarity of the req signal. when set, the req pin is active low: data must be input when req is low. when reset, the req pin is active high and data must be input when req is high. - imode[1...0] input mode. indicates which data input interface is used. the configuration of the 3 possible interfaces is shown below: when the ic is configured in mode 1 or 3, the can_setup register is used to configure the ic with repect to the data format. can_setup a/d converter setup address : 0x0d type: r/w software reset: nc hardware reset: 0 description: can_setup is used to configure the data serial in- terface. the register is only taken into account when the register sin_setup [1...0] = 3. also see sin_setup register./ - s16 when set, the slot count is 16. when re- set, the slot count is 32 but only the first 16 are extracted. - sam when set data is sampled on the falling edge of the dstr. when reset, the data is sampled on the rising edge of dstr - fir when set the first channel (left) is input when lrclkin=1. when reset, the first channel is input when lrclkin=0. - pad when set, data lrclkin is delayed by one cycle (padding mode). when the ic is configured with the s/pdif input, reg- ister can_setup must be set to 2 datain data input 7654 3 2 1 0 spdif pol imode [1...0] imode[1:0] mode 0 parallel input (dstr+data [7:0] + req) 1 serial input (dstr + sin + req) 2 reserved - not used 3 a/d input (dstr+lrclkin+req+sin; spdif input; pcm input 76543210 s16 sam fir pad 76543210
STA310 40/90 address : 0x0e type: wo software reset: na hardware reset: na description: data can be fed into the STA310 by using this register instead of the dedicated interface. there is no need to byte align the bitstream when using this register. 9.5 pcm configuration resisters pcmdivider divider for pcm clock address : 0x54 type: r/w software reset: und hardware reset: und description: the pcm divider must be set according to the formu- la below, where dac_sclk is the bit clock for the dac. when div is set to 0, dac_sclk is equal to dac_pcmclk: div = (dac_pcmclk/ (2 x dac_sclk)) -1 when the internal pll is used, dac_pcmclk=384 x fs or 256 x fs. if dac_pcmclk = 384 x fs, the for- mula becomes: div = (192 x fs/dac_sclk) -1 if dac_sclk is 32 x fs (common case with the 16 bit dac), div must be set to 5. pcmconf pcm configuration address: 0x55 type: r/w software reset: nc hardware reset: und description: pcmcross 76543210 pcm divider value mode description 5 dac_pcmclk = 384fs, dac is 16-bit mode 3 dac_pcmlk = 256 fs, dac is 16-bit mode 2 dac_pcmlk = 384 fs, dac is 32-bit mode 1 dac_pcmlk = 256 fs, dac is 32-bit mode 76543210 odr dif inv for scl prec[1:0] bitfield description ord pcm order: this bit is significant only when in 16-bit mode. when set, lsb is sent first. when reset, msb is sent first. dif pcm_diff: this bit is not significant in 16-bit. when set, indicates that the bits are not right-padded in the slot. when reset, ii is right padded. inv inv_lrclk: when set the polarty of lrclk is inverted: left channel is output when lrclk is high. when reset, the polarity of lrclk is such that the left channel is outout when lrclk is low. for format: this bit selects the data output format: when set, the sony format is chosen. when reset 0 the format is is format. scl inv_sclk: when set, the polarity of sclk is inverted, the pcm outputs and lrclk will be stable for the dacs on the falling edge of sclk. when reset, pcm outputs and lrclk are stable on the rising edge of sclk. prec[1:0] pcm precision 0: 16 bit mode (16 slots) 1: 18 bit mode (32 slots) 2: 20 bit mode (32 slots) 3: 24 bit mode (32 slots) 7 654 3 2 10 vcr clr[1:0] csw[1:0] lrs[1:0] pcm divider value mode description
41/90 STA310 address: 0x56 type: r/w software reset: nc hardware reset: und description: the pcmcross register only acts if bit pfc of reg- ister spdif_dtdi is set. 9.6 pdac and pll configuration registers sfreq sampling frequency address: 0x05 type: r/ws software reset: nc hardware reset: 0 description: this status register holds the code of the current sampling frequency. if the audio stream is encoded (dolby digital, mpeg) or packetized (dvd_lpcm), the sampling frequency is automatically read in the audio stream and written into this register by the au- dio dsp. the register is automatically updated by the dsp when it performs a down-sampling (for exam- ple, 96khz to 48khz). the dsp resets sfreq to 0. for pcm stream or cdda, this register is written to by the application. the value in sfreq corresponds to the following frequencies:. pllctrl pll contro l address: 0x12 type: r/w software reset: na hardware reset: 0x19 description: pll_data bitfield description lrs[1:0] cross left and right surround. csw[1:0] cross centre and subwoofer. clr[1:0] cross left and right channels. 00 : left channel is mapped on the left output, right channel is mapped on the right output. 01: left channel is duplicated on both outputs. 10: right channel is duplicated on both outputs. 11: right channel and left channel are toggled. vcr[1:0] these 2 bits manage the vcr outputs. 76543210 fs (khz) 46 44.1 32 - 96 88.2 64 - 24 22.05 value 0 1 2 3 4 5 6 7 8 9 fs (khz) 16 - 12 11.025 8 - 192 176.4 128 - value 10 11 12 13 14 15 16 17 18 19 765 4 3 210 sysclsck[1..0] oclk[2..0] bitfield value description oclk [2:0] configure pcmclk source and direction pcmclk pad direction -01 audio master clock from pcmlck pad. input 011 audio master clock from internal audio pll input 111 audio master clock from internal s/pdif receiver input -00 forbidden 010 audio master clock from internal audio pll output 110 audio master clock from internal s/pdif receiver output sysclc k[1:0] 0 system clock from clk pad output 1 system clock from clk pad divided by 2 2 system clock from internal system pll 3 system clock from internal system pll divided by 2
STA310 42/90 plldata address: 0x11 type: r/w software reset: na hardware reset: 0 description: data that must be written (has been read) at (from) the address specified by pll_add. pll_cmd pll command address: 0x1d type: r/w software reset: na hardware reset: 0 description: pll_add pll address address: 0x12 type: r/w software reset: na hardware reset: 0 description: ena_au_fracpll audio pll enable address: 0xb5 type: r/w software reset: 1 hardware reset: 0 description: this register is used to enable the audio pll of the STA310. this register must be always set to 1 after either a soft or hardware reset. au_pll_fracl_192 frac low coefficient address: 0xb6 76543210 7654 3 2 1 0 aupllctl syspllctl rwctl[1:0] bitfield description rwctl [1:0] configure pcmclk source and direction. 00 : no action is performed on the configuration registers of the level 1 01: read action of the configuration registers. during this phase, the content of a selectable (by pll_add) register of the level 1 is copied into the pll_data register. 10: write action of the configuration registers. during .this phase, the content of a selectable (by pll_add) register of the level 1 is copied into the pll_data register. 11: forbidden syspllctl system pll coefficients transfert 0: no transfer 1: transfer the data between the level 1 and the level 2 for the system pll aupllctl audio pll coefficient transfert 0: no transfer 1: transfer the data between the level 1 and the level 2 for the audio pll 76543210 address value address of plls configuration registers address 2: disable system pll 3: system pll frac low 4: system pll frac high 6: system pll n divider 7: system pll x divider 8: system pll m divider 9: system pll update 10: disable audio pll 11: audio pll frac low 12: audio pll frac high 14: audio pll n divider 15: audio pll x divider 16: audio pll m divider 17: udio pll update 7654321 0 ena_pll 76543210 fracl
43/90 STA310 type: r/w software reset: 0x34 hardware reset: und description: this register must contain a fracl value that en- ables the audio pll to generate a frequency of ofact*192khz for the pcmck. default value at soft reset assume: C oversampling factor (ofact) = 384. pcmlck = 384 x sf (where sf is the sampling frequency) C external crystal provide a clock running at 27mhz au_pll_frach_192 frac high coefficient address: 0xb7 type: r/w software reset: 0xec hardware reset: und description: this register must contain a frach value that en- ables the audio pll to generate a frequency of ofact*192khz for the pcmck. default value at soft reset assume: C oversampling factor (ofact) = 384. pcmlck = 384 x sf (where sf is the sampling frequency) C external crystal provide a clock running at 27mhz au_pll_xdiv_192 x divider coefficient address: 0xb8 type: r/w software reset: 0x01 hardware reset: und description: this register must contain a xdiv value that enables the audio pll to generate a frequency of ofact*192khz for the pcmck. default value at soft reset assume: C oversampling factor (ofact) = 384. pcmlck = 384 x sf (where sf is the sampling frequency) C external crystal provide a clock running at 27mhz au_pll_mdiv_192 m divider coefficient address: 0xb9 type: r/w software reset: 0x09 hardware reset: und description: this register must contain a mdiv value that enables the audio pll to generate a frequency of ofact*192khz for the pcmck. default value at soft reset assume: C oversampling factor (ofact) = 384. pcmlck = 384 x sf (where sf is the sampling frequency) C external crystal provide a clock running at 27mhz au_pll_ndiv_192 n divider coefficient address: 0xba type: r/w software reset: 0x01 hardware reset: und description: this register must contain a ndiv value that enables the audio pll to generate a frequency of ofact*192khz for the pcmck. default value at soft reset assume: C oversampling factor (ofact) = 384. pcmlck = 76543210 frach 76543210 xdiv 76543210 mdiv 76543210 ndiv
STA310 44/90 384 x sf (where sf is the sampling frequency) C external crystal provide a clock running at 27mhz au_pll_fracl_176 frac low coefficient address: 0xbb type: r/w software reset: 0x3 hardware reset: und description: this register must contain a fracl value that en- ables the audio pll to generate a frequency of ofact*176khz for the pcmck. default value at soft reset assume: C oversampling factor (ofact) = 384. pcmlck = 384 x sf (where sf is the sampling frequency) C external crystal provide a clock running at 27mhz au_pll_frach_176 frac high coefficient address: 0xbc type: r/w software reset: 0x9 hardware reset: und description: this register must contain a frach value that en- ables the audio pll to generate a frequency of ofact*176khz for the pcmck. default value at soft reset assume: C oversampling factor (ofact) = 384. pcmlck = 384 x sf (where sf is the sampling frequency) C external crystal provide a clock running at 27mhz au_pll_xdiv_176 x divider coefficient address: 0xbd type: r/w software reset: 0x01 hardware reset: und description: this register must contain a xdiv value that enables the audio pll to generate a frequency of ofact*176khz for the pcmck. default value at soft reset assume: C oversampling factor (ofact) = 384. pcmlck = 384 x sf (where sf is the sampling frequency) C external crystal provide a clock running at 27mhz au_pll_mdiv_176 m divider coefficient address: 0xbe type: r/w software reset: 0x09 hardware reset: und description: this register must contain a mdiv value that enables the audio pll to generate a frequency of ofact*176khz for the pcmck. default value at soft reset assume: C oversampling factor (ofact) = 384. pcmlck = 384 x sf (where sf is the sampling frequency) C external crystal provide a clock running at 27mhz au_pll_ndiv_176 n divider coefficient 76543210 fracl 76543210 frach 76543210 xdiv 76543210 mdiv 76543210 ndiv
45/90 STA310 address: 0xbf type: r/w software reset: 0x01 hardware reset: und description: this register must contain a ndiv value that enables the audio pll to generate a frequency of ofact*176khz for the pcmck. default value at soft reset assume: C oversampling factor (ofact) = 384. pcmlck = 384 x sf (where sf is the sampling frequency) C external crystal provide a clock running at 27mhz init_ram STA310 boot done address: 0xff type: ro software reset: 1 hardware reset: 0 description: this register is used to signal when the STA310 has finished to boot. after a soft reset or a hardware re- set, the host processor must wait until init_ram hold the value 1. the host can then start to configure the STA310 ac- cording to its application. pllmask pcmclk mask for half sampling frequency address: 0x18 type: w software reset: nc hardware reset: 0 9.7 channel delay set-up registers the six delay setup registers are used to set the rel- ative delays to the (up to) six loud speaker channels in order to give the sound effects of, for example, a large room or to compensate for the listener not being in the centre of the loud speaker system. the sum of the delays on the channels must be less than or equal to 35ms. the unit for the register delay contents is a group of 16 samples. each register value is chosen using the expression: desired channel delay*sampling frequency/16 sam- ples and taking care to ensure that the sum of the de- sired channel delays is not more than 35ms. for example, when the sampling frequency is 48khz, the sum of the values programmed in the six delay registers must be less than or equal to: 35 ms * 48 khz /16 samples = 105. when only one surround channel is present (in pro logic or other mode), the right surround delay must be cleared, and the left delay channel is used for both surround channels. ldly left channel delay address: 0x57 type: r/w software reset: nc hardware reset: und 7654321 0 ram_init 7654321 0 half_fs bitfield description half_fs if the incoming bitstream is encoded with half sampling frequency, the device generates a pcm clock (for audio dac) 1: at 256 x half_fs or 384 x half_fs (half_fs is equal to 24khz, 22.05khz, 16khz). 0: at 256 x fs or 384 x fs (fs is equal to 48khz, 44.1khz, 32khz). this function is mainly use for dac frequency adaptation. 76543210
STA310 46/90 delay on left channel, expressed in number of group of 16 samples. ldly = delay (ms) * fs (khz) / 16 rdly right channel delay address: 0x58 type: r/w software reset: nc hardware reset:und delay on right channel, expressed in number of group of 16 samples. rdly = delay (ms)*fs (khz)/16 cdly centre channel delay address: 0x59 type: r/w software reset: nc hardware reset: und description: delay on center channel, expressed in number of group of 16 samples. cdly = delay (ms) * fs (khz) / 16 subdly subwoofer channel delay address: 0x5a type: r/w software reset: nc hardware reset: und description: delay on subwoofer channel, expressed in number of group of 16 samples. subdly = delay (ms) * fs (khz) / 16 lsdly left surround channel delay address: 0x5b type: r/w software reset: nc hardware reset: und delay on left surround channel, expressed in number of group of 16 samples. lsdly = delay (ms) * fs (khz) / 16 rsdly right surround channel delay address: 0x5c type: r/w software reset: nc hardware reset: und description: delay on right surround channel, expressed in num- ber of group of 16 samples. rsdly = delay (ms) * fs (khz) / 16. when only one surround channel is used, this regis- ter must be reset at initialization. lvdly left vcr channel delay address: 0xaf type: r/w software reset: nc hardware reset: und description: delay on left vcr channel, expressed in number of group of 16 samples. lsdly = delay (ms) * fs (khz) / 16 76543210 76543210 76543210 76543210 76543210 76543210
47/90 STA310 rvdly right vcr channel delay address: 0xb0 type: r/w software reset: nc hardware reset: und description: delay on right vcr channel, expressed in number of group of 16 samples. rsdly = delay (ms) * fs (khz) / 16. when only one vcr channel is used, this register must be reset at initialization. update pcm delay update address: 0x5d type: r/w software reset: 0 hardware reset 0 description: 9.8 spdif output set-up spdif_cmd spdif control address: 0x5e type: r/w software reset: nc hardware reset: und this register controls the spdif mode: description: spdif_cat category code 76543210 76543210 tm dly bitfield description dly this bit must be set to 1 to force the dsp to update its delays values (read from the audio delay registers). 0: delay values held in the audio delay registers are not updated in the dsp (i.e. the dsp will keep the delay values set previously) 1: the delay values held in the audio delay registers are updated in the dsp (i.e. the dsp will use the new values). this bit is automatically reset to zero after it the update has been carried out. tm set to 0 765432 1 0 aux reserved spdif_mode[1:0] bitfield description spdif_mode[1:0] aux = 0 00: off, the iec60958 is not working and the output line is idle, 01: mute, the outputs are pcm null data, 10: pcm, the outputs are pcm data and only the left/right channels are transmitted, 11: emc, in this "encoded" mode the compressed bitstream is transmitted in iec61937 standard. spdif_mode[1:0] aux = 1 10: pcm, the outputs are pcm data and only the "vcr" channels are transmitted. all other values are reserved. 76543210 catcode
STA310 48/90 address: 0x5f type: r/w software reset: nc hardware reset: und description: the table below defines the category codes, values not listed are reserved. spdif_conf spdif pcmclk divider address: 0x60 type: r/w software reset:nc category code description 0 0 0 0 0 0 0 1 0 0 0 0 0 0 x x x 0 0 0 0 x x x 1 0 0 0 general experimental reserved solid state memory 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 x x x x 1 0 0 broadcast reception of dig. audio broadcast reception of dig. audio broadcast reception of dig. audio broadcast reception of dig. audio broadcast reception of dig. audio japan united states europe electronic software delivery all other states are reserved 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 x x x x 0 1 0 digital / digital converters and signal processing digital / digital converters and signal processing digital / digital converters and signal processing r digital / digital converters and signal processing digital / digital converters and signal processing pcm encoder/decoder digital sound sampler digital signal mixe sample rate converter all other states are reserved x x 0 0 1 1 0 x x 1 0 1 1 0 x x x 1 1 1 0 a/d converter w/o copyright a/d converter w/ copyright (using copy and l bits) broadcast reception of dig. audio 0 0 0 0 0 0 1 0 0 0 1 0 0 1 x x x x 0 01 laser optical cd - compatible with iec 908 laser optical cd - not compatible with iec 908 (magneto optical) laser optical all other states are reserved 0 0 0 010 1 0 0 0 110 1 x x x x101 musical instruments, microphones, etc. musical instruments, microphones, etc. musical instruments, microphones, etc. synthesizer microphone all other states are reserved 0 0 0 0 0 1 1 0 0 0 1 0 1 1 x x x x 011 magnetic tape or disks magnetic tape or disks magnetic tape or disks dat digital audio sound vcr all other states are reserved x x x x111 reserved 7 0 1 only cat. codes xxxx100, xxx1110, xxxx001 -> l bit original, commercially pre-recorded data no indication of 1st generation or higher 7 0 1 all other categories no indication of 1st generation or higher original, commercially pre-recorded data 76543210 lat sm=0 rnd div[4:0]
49/90 STA310 hardware: reset:und description: the table below shows the relationship between the value of the iec divider and the value of the pcm divider. spdif_status spdif status bit address: 0x61 type: r/w software reset: nc hardware: reset und description: bitfield description div[4:0] this field is the dac_pcmclk divider. it must be set according to the formula: in 16 bit mode: iecdiv=(1+pcmdiv)/2-1; in 32 bit mode: iecdiv=pcmdiv rnd this bit is used to have a "16-bit rounding" on the spdif (when in pcm mode): 0: no rounding, 1: rounding. this bit has no effect on the precision of analogue data sm sync mute mode, must be set to zero. lat configures the latency mode between the spdif output (in mode compressed) and the audio output. 0: auto-latency: the latency is the transmission time for 2/3 of the payload, plus the time to decode an audio block. for mpeg auto-latency, the latency is the following time depending of the sampling frequency in the incoming bitstream: mpeg 48khz: 20.90ms, mpeg 44.1khz: 22.95ms, mpeg 32khz: 32.53ms. 1: user-programmable latency - the spdif_latency register is used. pcm divider value mode description iec divider value 5 dac_pcmclk = 384fs, dac is 16-bit mode 2 3 dac_pcmlk = 256 fs, dac is 16-bit mode 1 2 dac_pcmlk = 384 fs, dac is 32-bit mode 2 1 dac_pcmlk = 256 fs, dac is 32-bit mode 1 76543210 sfr pre cop com
STA310 50/90 this register is used to set the value of the status bit in the iec958 data stream. spdif_rep_time spdif repetition time of a pause frame address: 0x75 type: r/w software reset: nc hardware: reset: und description: in compressed mode, a burst of pause frames is sent when there are no more data to transmit (due to an error or a gap in the incoming bitstream, for example). this register sets the size of a pause frame in iec frames: dolby digital =4, mpeg=32 and dts=3. spdif_latency latency value address: 0x7e type: r/w software reset: nc hardware: reset: und description: if bit lat of register spdif_conf is set, a delay can be configured between the output of iec61937 in com- pressed mode and the output of the audio decoder. to configure a latency (in unit of seconds) this register has to be set according the following formula: value = l x fs/8 where, l=latency in s and fs=sampling frequency in hz bitfield description com compress data bit. 1: compressed mode 0: non compressed mode. cop 1: copy allowed 0: copy not allowed pre 1: output has pre-emphasis 0: output does not have pre-emphasis sfr 0000: if sampling frequency = 44.1khz 0010: if sampling frequency = 48khz 0011: if sampling frequency = 32khz 1010: if sampling frequency = 96khz 76543210 76543210 value
51/90 STA310 the minimum latency delay is 0; the maximum laten- cy delay is the time to decode a frame: spdif_dtdi spdif data-type information address: 0x7f type: r/w software reset: nc hardware: reset: und description:: autodetect_ena s/pdif autodetection enable address: 0xe0 type: r/w software reset: 0 hardware: reset: und description: the feature is only available for STA310 cut 2.0. this register is used to enable the autodetection on the s/ pdif. when high, the autodetection is present. when low, autodetection is disable. the STA310 cut 2.0 is able to detect the following au- dio format changes on the s?pdif input. the host must respond to the rst and lck interrupt in order for the STA310 to take into account the change of the audio format. autodetect_sens s/pdif autodetection sensitivity address: 0xe1 type: r/w software reset: 0 hardware: reset: und description: the feature is only available for STA310 cut 2.0. this register is used to configure the autodetection sensi- tivity. the lower is sens, the faster is the autodetec- tion. typical value is 0. autodetect_ align s/pdif autodetection alignement address: 0xe2 type: r/w software reset: 0 hardware: reset: und description: bitfield description value dolby digital: l = 1536 samples / sampling frequency mpeg: l = 1152 samples / sampling frequency 76543210 pfc dtd inf bitfield description dtdi[4:0] in dolby digital mode: 4 3 2 1 0 0 0 bsmod [2..0] in mpeg mode: 4 3 2 1 0 000drk dtd 1: data-type dependent information used for the spdif in compressed mode, can be set by the user. refer to iec958 standard for more information. 0: transmitted dtdi are extracted from the stream. pfc 1: pcmcross function enabled 76543210 ena from to ac3 pcm ac3 mpeg mpeg ac3 mpeg pcm pcm ac3 pcm mpeg 76543210 sens
STA310 52/90 the feature is only available for STA310 cut 2.0. this register is used to configure the left/right sample alignement of the s/pdif. typical value is 10 9.9 audio command registers softreset soft reset address: 0x10 type: w0 software reset: na hardware: reset: na description: when bit 0 of this register is set, a soft reset occurs. the command registers and the interrupt registers listed below are cleared. the decoder goes into idle mode and the volumes are cleared. command registers: mute, run, play, skip_mute_cmd and skip_mute_value interrupt registers: inte, int and error play play address: 0x13 type: r/w software reset: 0 hardware: reset: 0 description: the play command is treated according to the state of the decoder: n when in idle mode, the play value is not taken into account by the decoder. n when in init mode, the play value is not taken into account by the decoder. n when in decode mode, play enables the decoding, see table below: mute mute address: 0x14 type: r/w software reset: 0 hardware: reset: 0 description: the mute command is handled differently according to the state of the decoder: n when in idle mode after hardware reset, setting mute to 1 automatically runs the dac_sclk and dac_lrclk clocks and outputs them to the dacs. n when playing, setting mute to 1 mutes the pcm outputs. n the mute register has no effect on the spdif output. run run decoding address: 0x72 76543210 76543210 play play value mute value dac_sclk, dac_lrclk state dac_pc mout decoding 0 0 not running 0 no 0 1 running 0 no 1 0 running decoded samples yes 1 1 running 0 yes 7654 321 0 mute 7654321 0 run
53/90 STA310 type: r/w software reset: 0 hardware reset: 0 description: this register enables to exit from idle mode. after a soft or hard reset the decoder is in idle mode. it stays in this mode until the run is set. in run mode the decoder takes into account the state of all the configuration registers and begins to de- code. the run register can only be reset by the softre- set command. skip_mute_cmd skip or mute commands address: 0x73 type: r/w software reset: 0 hardware reset: 0 description: this register cannot be used in mp3 decoding mode.the register is taken into account at a begin- ning of decoding a frame. skip_mute_value skip frames or mutes blocks of frame address + 0x74 type: r/w software reset: 0 hardware reset:0 description: the value in this register gives either the number of frames to skip or the number of blocks during which the decoder will be stopped. this is used in conjunc- tion with register . 9.10 interrupt register inte interrupt enable address: 0x08 - 0x07 type: r/w software reset: 0 hardware reset: 0 description: this register is used to enable each interrupt inde- pendently. setting a bit in the register enables the corresponding interrupt. int interrupt address: 0x0a - 0x09 type: ro software reset: 0 hardware reset:0 765 4 3210 reserved mute reserved pau blk skp smut value description smut, mute if one or both of these bits is 1 then the decoder continues the normal decoding process, but the output samples are soft- muted to zero. when both these bits are 0 muting is disabled and the decoder plays the incoming frame. skp skip frame. the decoder skips the number of frames programmed in register blk pause block. the decoder introduces a delay equal to the number of blocks programmed in register pau the decoder is stopped whilst this bit is 1. reserved set to 0. 7654321 0 7654321 0 @0x08 inte[15:8] @0x07 inte[7:0] 7654321 0 @0x0a inte[15:8] @0x09 inte[7:0]
STA310 54/90 description: these registers indicate which interrupt occurred. provided an interrupt is enabled through the register inte, if the corresponding bit of int is set, the corresponding interrupt has occurred. the signal irq is activated whenever one of the bits of int become set. depending on the nature of the con- dition, clearing a bit in int register is performed by ei- ther reading the msb of int register, or by reading the msb of the associated condition registers (see below). this register is reset by software reset. the table below shows the interrupt nature indicated by each bit.. notes: 1. cleared when a reset occurs or when the msb of the in- terrupt register is read 2. cleared when a reset occurs or when the msb of the corresponding register is read. affected registers are listed in the following table 3. only available in STA310 cut 2.0 9.11 interrupt status registers sync_status synchronization status address: 0x40 type: ro software reset: und hardware reset: und bit numer name condition signalled 0 syn change in synchronization status (1) 1 hdr valid header registered (1) 2 err error detected (1) 3 sfr sampling frequency changed (2) 4 dem de-emphasis changed (2) 5 bof first bit of new frame at output stage (2) 6 pts first bit of new frame with pts at output stage (2) 7 anc not implemented 8 pcm pcm output underflow (2) 9 fbf frame buffer full: the frame buffer memory contains 2 frames: one decoded, and one parsed for next decoding 10 fbe frame buffer empty: the frame buffer memory contains 1 frame which begins to be decoded. the next frame begins to be parsed 11 fio fifo input has overflowed (2) 12 rst (3) the STA310 has detected a change in the incoming audio format. the soft reset produce must be applied and the device must be re-initialized according to the new audio format detected. registers decodesel (0x4d) and streamsel (0x4c) contain the new audio format (1) 13 lck (3) a break has occurred in the s/pdif stream causing the internal s/pdif pll to get unlocked. the soft reset procedure must be applied and the device must be re-initialized according to the current audio format decoding contained in the registers decodesel (0x4d) and srtreamsel (0x4c). (1) 14 usd reserved 15 tbd reserved address name 0x0f error 0x40 syncstatus 0x41 anccount 0x42 head 4 0x46 pts [32] 7654321 0 pac fra bit numer name condition signalled
55/90 STA310 description: this register indicates the status of the audio parser for synchronization. it is used in conjunction with packet_lock and synck_lock registers. on read the synchronization status interrupt bit is cleared (int.syn is cleared). anccount ancillary data address : 0x41 type: ro software reset: und hardware reset: und description: this value gives the number of ancillary data in the stream. the ancillary data interrupt bit anc of the register is cleared by a read. head4 header 4 register ac_3 mpeg_2 other address: 0x42 type: ro software reset: und hardware reset: und description: this register contains header data head[31:24]. the contents depend on the type of the frame.head4[7:3] = 00000, in all cases. when the host reads this register, the corresponding interrupt bit (hdr) is cleared. dolby digital mpeg-2 other in all other types of frame head4[2:0] = 000 head3 header 3 register address: 0x43 type: ro software reset: und hardware reset: und description: bitfield description fra frame status 0 0: research audio synchronization 0 1: wait for confirmation - a synchro word has been detected but the parser has not yet detected sync-lock+1 synchro words. 1 0: synchronized - sync_lock + 1 synchro words have been detected 1 1: not used pac packet status 0 0: research packet synchronization word 0 1: wait for confirmation - - a synchro word has been detected but the parser has not yet detected packet_lock+1 synchro words. 1 0: synchronized - packet_lock + 1 synchro words have been detected 1 1: not used 76543210 76543 2 1 0 00000 bsmod 000000 dr k 0000 0 000 bitfield description head4[2:0] bsmod if an dolby digital frame bitfield description head4[2] 0 head4[1] dr=1 dynamic range exists head4[0] k=0 in normal mode, k=1 in karaoke mode. 76543210 0 0 0 dtype
STA310 56/90 this register contains header data head[23:16].head3[7:5]=000, in all cases head3[4:0] = dtype dtype is the data type and is defined as follows: this register can not detect the data-type of data in a stream. headlen frame length addres s: 0x44 - 0x45 type: ro software reset: und hardware reset: und description: the headlen register contains the bit length of the compressed data frame head[15:0]. header reg- isters are all updated as soon as the decoder begins to decode a frame. pts pts address: 0x46 to 0x4a type: r/w software reset: und hardware reset: und description: when the pts interrupt is activated, a new pts val- ue is stored in this register. once the pts[32] value is read bit pts of the pts register is cleared. error error code address + 0x0f type: ro software reset: 0 hardware reset:0 description: this is a status register, when read by the st20, this and the corresponding interrupt register are cleared. this 7-bit register is anded with 0x7f to get the cor- rect value. the value in the error register indi- cates the type of error that has occurred. these errors are defined in the table below. bit description dtype 0000: null data or linear pcm 0001: dolby digital 0100: mpeg-1 layer i 0101: mpeg-1 layer ii or mpeg-2 word extension 0110: mpeg-2 layer ii with extension 1001: mpeg-2 layer ii low sample rate (11) 1011: dts-1 (frame size 512) (12) 1100: dts-2 (frame size 1024) (13) 1101: dts-3 (frame size 2048) 76543210 headlen[15:8] headlen[7:0] 76 54321 0 0x46 pts[32] 0x47 pts[31:24] 0x48 pts[23:16] 0x49 pts[15:8] 0x4a pts[7:0] 76543210 error name value (decimal) dolby digital decoding no error 0 expand_delta_past_end_array 1 xdcall_try_to_reuse_remat_flg 2 xdcall_try_to_reuse_coupling_st ra 3 xdcall_cant_couple_in_dual_mode 4 xdcall_try_to_reuse_cpl_leak 5 xdcall_try_to_reuse_snr 6 xdcall_try_to_reuse_bit_alloc 7 xdcall_try_to_reuse_coupling_ex ponent_stra 8 xdcall_try_to_reuse_exponent_s tra 9 xdcall_try_to_reuse_lfe_exponen t_stra 10 xdcall_chbwcod_is_too_high 11
57/90 STA310 9.12 decoding algorithm registers the table below shows how the streamsel and decodsel registers should be programmed for dif- ferent types of bitstream. table 9. streamsel and decodesel programming definitions bsi_err_rev 12 bsi_err_chans 13 crc_not_valid 14 packet synchronization synchro_packet_not_found 16 bad_mpegi_reserved_word 17 bad_mpeg2_reserved_word 18 bad_lpcm_synchro 19 unknown_stream_id 20 marker_error 21 unknown_sub_stream_id 22 iec958_input_mismatch_conf 23 iec958_mpeg2_layeri_not_supporte d 24 iec958_pause_frame_not_supporte d 25 iec958_bad_data_type_dependant 26 mismatch _host_sel_configuration 27 audio synchronization synchro_audio_not_found 32 bad_crc_ac3 33 bad_lpcm_quantization_wordleng th 34 bad_audio_sampling_frequency 35 bad_mpeg_layer 36 mpeg_bitrate_free_format 37 not_supported_ac-3_frmsizecod 38 bad_crc_mpeg_extended 39 bad_mpeg_extended_reserved_bit 40 mpeg_extended_sync_not_found 41 mpeg_extended_length_too_small 42 bad_samples_per_channel 44 bad_frame_bit_size 45 mpeg decoding mpeg_extension_error 48 mpeg_mc_mute 49 not used 50 not used 51 mpeg_layer_error 52 mpeg_chconfig_error 53 mpeg_mc_prediction_error 54 mpeg_crc_error 55 mpeg_ext_crc_error 56 mpeg_too_small_for_mc_header 57 error name value (decimal) mpeg_bitrate_error 58 mp3 decoding crc_error 01 data_available_error 02 anc_partial_read_error 03 anc_not_read_error 04 bad_id_and_idex_values 33 layer_is_nor_layer3 34 bad_audio_sampling_freq 35 free_format_not_supported 36 bit_rate_not_supported 37 big_value_error 48 mode_change_error 49 fs_change_error 50 miscellaneous iec_958_read_error 64 mpeg_fb_bypass_area_error 65 skipping_bits_in_fb_error 66 latency_too_big 67 skip_mute_error 68 unknow_sfreq_for_latency 69 latency_too_small 70 bad_input_chan 71 invalid_alpha_coeff 72 streamsel (0x4c) decodsel (0x4d) mode 0 0 mpeg2 pes carrying dolby digital (atsc) 0 1 mpeg2 pes carrying mpeg1 frames 0 2 mpeg2 pes carrying mpeg2 frames 1 0 mpeg2 pes carrying dolby digital frames for dvd video error name value (decimal)
STA310 58/90 decodsel decoding algorithm address: 0x4d type: r/w software reset: nc hardware reset: und description: this register identifies the audio data-type. streamsel stream selection address: 0x4c type: r/w software reset: nc hardware reset: und description: 9.13 system synchronization registers packet_lock packet lock address: 0x4f type: r/w software reset: nc hardware reset: und 1 2 mpeg2 pes carrying mpeg2 frames for dvd video 1 3 mpeg2 pes carrying linear pcm for dvd video 2 1 mpeg1 packet carrying mpeg1 audio 30 dolby digital frames elementary streams 3 1 mpeg1 frame elementary streams 3 2 mpeg2 frame elementary stream 3 3 stereo pcm (16bits samples) and pcm2 channels 3 4 pink noise generator 3 5 cdda (stereo pcm 16 bits samples) 3 7 activate pcm beep tone 3 9 mp3 elementary streams 5 0 iec61937 input with dolby digital frames 5 1 iec61937 input with mpeg1 frames 5 2 iec61937 input with mpeg2 frames 5 6 iec61937 input with dts frames 6 3 linear pcm for dvd audio 7 65432 1 0 dec bitfield description dec[3:0] 0000: dolby digital decoding 0001: mpeg1 0010: mpeg2 0011: pcm/lpcm 0100: pink noise generator 0101: cd_da 0111: pcm beep tone generator 1001: mp3 76543210 strsel bitfield description strsel 000: pes 001: pes dvd video 010: packet mpeg1 011: elementary stream/iec60958 100: reserved 101: spdif iec61937 110: pes dvd audio 7654321 0
59/90 STA310 description: this register specifies the number of supplementary packet synchro words that the packet parser must detect before it is considered as synchronized, and can send data to the audio parser (max=1, min=0). in this way, stream data can not be sent to the audio parser instead of packet sync words. packet_lock = 0: the packet parser is synchro- nized when it has detected one packet synchro word. packet_lock = 1: the packet parser is synchro- nized when it has detected two packet synchro words. id_en enable audio id address: 0x50 type: r/w software reset: nc hardware reset:und description: if set to 1, the audio decoder decodes only the stream corresponding to the stream-id or sub-stream-id of the packet layer. this selection is done through audio_id or audio_id_ext registers. if set to 0, the decoder decodes all the audio packets. i d audio id address : 0x51 type: r/w software reset: nc hardware reset: und description: when decoding packets, it is possible to specify an identifier for a selected program. audio_id must be written with the packet id. this feature is enabled when the register audio_id_en is set, and only packets with matching id are decoded. for mpeg1 packets or pes, the 5 lsb bits are sig- nificant. for dvd pes (lpcm, dolby digital or mpeg), the 3 lsb bits are significant (see audio pack definition in dvd specifications). these bits correspond to the stream number defined in the stream_id field of the audio packet header, except for dvd, dolby digital or lpcm packets, where they correspond to the stream number defined in the sub_stream_id field. id_ext audio extension address + 0x52 type: r/w software reset: nc hardware reset: und description: the 3 lsb bits of this register are significant. in case of dvd mpeg2 audio with extension bitstream (see dvd specifications), this register is used to select the stream defined in the stream_id of the packets containing mpeg2 extension bit stream data. sync_lock sync lock address: 0x53 type: r/w software reset: nc hardware reset: und description: this register specifies the number of supplementary audio synchro words that the audio parser must de- tect before it is considered as synchronized, and can send data to the decoder. in this way, stream data can not be sent to the decod- er instead of audio sync words. max value = 3; min value = 0. sync_lock = 0, the audio parser is syn- chronized when it has detected one audio synchro word. sync_lock = n > 0, when the audio parser has detected one synchro word, it waits until it de- tects n supplementary audio sync words. 7654321 0 7654321 0 7654321 0 7654321 0
STA310 60/90 when it has detected (sync_lock+1) sync words, it sends the data to the decoder. 9.14 post decoding and pro logic registers pdec1 post decoder register address: 0x62 type: r/w software reset: nc hardware reset: und description: this register controls the post decoder operations. pl_ab pro logic auto balance address : 0x64 type: r/w software reset: nc hardware reset: und description: pl_dwnx pro logic decoder downmix address : 0x65 type: r/w software reset: nc hardware reset: und description: prologic decoder support only 4 sampling frequen- cies: 48khz, 44.1khz, 32khz, 22.05khz. if we active prologic with sampling frequency differ- ent from those frequencies, the decoder will be auto- matically disable the prologic call. ocfg output configuration address: 0x66 765432 1 0 vmax dem dcf db pvirt mpeg_dr pl bitfield description pl when high pro logic decoding is forced, when low the prologic decoder is automatically enabled when the stream contains the info that it is prologic encoded mpeg_dr when high enable mpeg dynamic range. db when high the "double stereo" procedure is enabled. double stereo is a copy of left/right channels on to left/right surround channels in order to have a pseudo 5 -channel decoder effect. dcf when set the dc filter is activated.. when reset, it is disabled. dem when set the de-emphasis filter is activated.. when reset, it is disabled. 765432 1 0 pl_ws pl_ab bitfield description pl_ab when high, select the auto-balance function (used to track out gin mismatches between lt and rt).when low, disable the autobalance function pl_ws when high, enable wide surround mode. the wide surround option is provided for users who plan to do further post- processing of the pro logic outputs, and want to fold the lowpass filtering of the surround channel into their downstream processing lowpass filtering and b-type shelf filtering are both disabled. when low, disable ide surround mode. 7654 3 2 1 0 lfe_byp pl_dwnx[2:0] bitfield description pl_dwnx [2:0] 0,1,2: pro logic disabled 3: 3/0 (l, r, c) three stereo 4: 2/1 (l, r, ls) phantom 5: 3/1 (l, c, r, ls) 6: 2/2 (l, r, ls, rs) phantom 7: 3/2 (l, c, r, s, s) lfe_byp 0: lfe channel is clear 1: lfe channel is bypassed 7 6 543210 lfe_byp boost ocfg[2:0]
61/90 STA310 type: rw software reset: nc hardware reset: und description: 6 output configurations are provided that redirects bass on subwoofer channel, and applies some filters on channels. the description is provided in the output configura- tion section. this register is used to indicate the output configura- tion chosen. - lp means low pass filter - hp means high pass filter note: 1. in configuration 3 with subwoofer enabled, the output of the subwoofer is 10db greater than expected. therefore when using this mode, the subwoofer output level needs to be attenuated 10db in order to match the subwoofer output levels of other bass management configurations. in general be carefull while using the boost option since it has the potential of causing the woofer output to over- load dwsmode bitfield conf meaning description ocfg[2:0] bass management configuration according to the bass direction scheme from dolby. for configurations 2,3,4 the subwoofer can be output is bit lfe asset to high. for all other configurations, the lfe bit has no effect. 0 all all channels are rounded according to the selected output precision, (24b -> 16b, 24 -> 18b.) and scaled (volume control) only. 1 lsw low frequencies are extracted from the six input channels and redirected to the subwoofer. sub = lp(l+r+ls+rs+c+lfe).low frequencies are removed from all channels l = hp(l), r = hp(r), c = hp(c), ls = hp(ls), rs = hp(rs). 2 llr low frequencies are extracted from c, lfe, ls and rs channels and redirected to left and right channels: c = hp (c), rs = hp (rs), ls = hp(ls), l = l + lp (c+lfe+ls+rs), r = r + lp(c+lfe+ls+rs). if subwoofer is output, sub = lp (lfe+c+ls+rs). 3 (1) slp low frequencies are redirected to the left, right and surround channels or cab be output on the subwoofer. if sub-woofer is output, sub = lfe, l = l + lp(c), r = r + lp(c), ls = ls, rs = rs if sub-woofer is not output, l = l + lp(c) + lfe, r = r + lp(c) + lfe, ls = ls + lfe, rs = rs + lfe. 4 simp simplified configuration. low frequencies are exrtacted from c, ls, rs and lfe. if subwoofer is output, sub = lp(c+ls+rs) + lfe, l = l, r = r. if sub-woofer is not output, sub = lfe, l = l + (c+ls+rs), r = r + (c+ls+rs). 5 byp bypass, all channels are directly routed to pcm outputs. 6 configuration 1 without filters. boost (1) channel level, enables boost: if ocfg_num = 2 : 0 : no +12db boost on left and right channels 1 : +12db boost on left and right channels when configuration = 3 : if sub-woofer is output : 0 : no +4db boost on all channels 1 : +4db boost on all channels if sub-woofer is not output : 0 : no +8db boost on all channels 1 : +8db boost on all channels lfe_byop 0; lfe channel is clear 1: lfe channel is bypassed
STA310 62/90 downsampling filter address: 0x70 type: r/w software reset: nc hardware reset: und description: this register controls the downsampling filter for the lpcm video, lpcm audio modes. when decoding a 96khz dvd-lpcm stream, it might be necessary to downsample the stream to 48khz . 9.15 bass redirection registers volume0 volume of first channel address: 0x4e type: rws software reset: 0 hardware reset: und description: this register reads or writes the attenuation that is applied to the channel selected by chan_idx. the volume of the left channel can be set up with a 0.5db step. n if chan_idx = 0, then volume0 can be written with the attenuation that will be applied to left channel. n if chan_idx = 1, then volume0 can be written with the attenuation that will be applied to center channel. n if chan_idx = 2, then volume0 can be written with the attenuation that will be applied to left surround channel. n if chan_idx = 5, then reading volume0 provides the attenuation that is applied to left channel. n if chan_idx = 6, then reading volume0 provides the attenuation that is applied to center channel. n if chan_idx = 7, then reading volume0 provides the attenuation that is applied to left surround channel. n other values of chan_idx are reserved. volume1 volume of second channel address: 0x63 type: rws software reset: 0 hardware reset: und description: this register reads or writes the attenuation that is applied to the channel selected by chan_idx. the volume of the right channel can be set up with a 0.5db step. n if chan_idx = 0, then volume1 can be written with the attenuation that will be applied to right channel. n if chan_idx = 1, then volume1 can be written with the attenuation that will be applied to subwoofer channel. n if chan_idx = 2, then volume1 can be written with the attenuation that will be applied to right surround channel. n if chan_idx = 5, then reading volume1 provides the attenuation that is applied to right channel. n if chan_idx = 6, then reading volume1 provides the attenuation that is applied to subwoofer channel. n if chan_idx = 7, then reading volume1 provides the attenuation that is applied to right surround channel. n other values of chan_idx are reserved. 76543210 value mode 0 automatic (according to bitstream) 1 force downsampling 2 suppress downsampling 76543210 avol0 7654321 0 avol1
63/90 STA310 chan_idx channel index address: 0x67 type: r/w software reset: 4 hardware reset: und description: this register identifies the pair of channels and the type of access: n to read a volume, the register chan_idx must be set to the appropriate value. the dsp indicates that the attenuation is readable through registers volume0 and volume1 by changing automatically the chan_idx to value 4. n to write a volume, the attenuation of the pair of channel should be written in volume0 and volume1 registers. then the chan_idx register is written to the appropriate value. the attenuation is updated on the next audio block and chan_idx value is automatically changed to 4. 9.16 dolby digital configuration registers ac3_decode_lfe decode lfe address: 0x68 type: r/w software reset: nc hardware reset: und description: when this register is set to 1, the device decodes lfe channel (if present). ac3_comp_mod compression mode address + 0x69 type: r/w software reset: nc hardware reset: und description: the value of this register defines the compression mode. in custom a mode, the dialog normalization function is not done by the audio decoder, it has to be done by an external analog part. in all other modes the normalization is done by audio decoder. 765432 1 0 reserved chan_idx bitfield value channel pair access comment chan_i dx 0 left and right write 1 center and subwoofer write 2 left surround and right surround write 3 reserved reserved 4 no pair selected none indicates that volume can be read or written 5 left and right read 6 center and subwoofer read 7 left surround and right surround read 7654321 0 76543210 value meaning 0 custom a (analog) 1 custom d (digital) 2 line out 3 rf mode
STA310 64/90 ac3_hdr high dynamic range address: 0x6a type: r/w software reset: nc hardware reset: und description: this register corresponds to the dynamic range scale factor for high level signals, also called cut fac- tor in the dolby specifications. hdr = 255 * cut factor (in decimal), where the cut factor is a fractional number between 0 and 1. it is used to scale the dynamic range control word for high-level signals that would otherwise tend to be re- duced. when hdr = 0xff (cut factor = 1.0), the high level sig- nals reduction is the one given in the stream. a value of zero disables the high-level compression. this word is ignored if the compression mode is set to rf mode. ac3_ldr low dynamic range address : 0x6b type: r/w software reset: nc hardware reset: und description: this register corresponds to the dynamic range scale factor for low level signals, also called boost factor in the dolby specifications. ldr = 255 * boostfactor (in decimal), where the boost factor is a fractional number between 0 and 1.0. the boost factor scales the dynamic r ange con- trol-word for low-level signals that would otherwise tend to be amplified. when ldr = 0xff (boost factor = 1.0), and the low level signals amplification is maximum. a value of zero disables the low-level amplification. this word is ignored if the compression mode is set to rf mode. ac3_rpc repeat count address + 0x6c type: r/w software reset: nc hardware reset: und description: when a crc error is detected, previous blocks can be repeated or muted. this register specifies the number of audio blocks to repeat before muting. if this is zero, then blocks are muted until the next frame is decoded ac3_karamode karaoke downmix audiobaseaddress + 0x6d type: r/w software reset: nc hardware reset: und description: downmix mode when a karaoke bit stream is re- ceived. a karaoke bitstream can be composed of 5 chan- nels, which are: l (left), r (right), m (music), v1(vocal 1), v2 (vocal 2). there are two major modes when receiving a karaoke bitstream: aware and capable. when in 'aware' mode ( karamode = 0), a pre- defined downmix is applied on all incoming channels. when in 'capable' mode ( karamode = 4, 5, 6, 7), the user can choose to reproduce or not the two in- 76543210 76543210 76543210 76543210
65/90 STA310 coming vocal channels, v1 and v2. an additional mode is added ( ac3_karamode = 3) to allow multi-channel reproduction. in this case, the downmix specified by the ac3_downmix and ac3_dualmode registers is applied. the following table summaries the different modes: left = output channel, right = output channel, l, r, m, v1, v2 = input channels (coded in dolby digital karaoke bitstream), clev = center mix level (value provided in the bit- stream), slev = surround mix level (value provided in the bit- stream). for further information ref. to annex c of atsc standard digital audio compression (ac-3). ac3_dualmode dual downmix address : 0x6e type: r/w software reset: nc hardware reset: und description this register allows additional downmix to be set when in 2/0 output mode or when receiving a dual mode incoming bitstream (example: a disk with 2 dif- ferent languages on channel 1 and channel 2). in the following table, channel 1 and 2 represent the output channels after downmix performed with ac3_downmix. this register enables mono downmix when ac3_downmix = 2 and ac3_dualmode = 3. ac3_downmix downmix address: 0x6f type: r/w software reset: nc hardware reset: und description:. note: in notation, 3/2 represents 3 front speakers and 2 surround speakers. ac3_status0 value mode comment 0 aware left = l + clev*m + slev*v1, right = r + clev*m + slev*v2 1 not used 2 not used 3 multicha nnel consider bitstream as multi-channel: perform downmix according to downmix and dualmode registers 4 capable do not reproduce v1, v2: left = l + clev*m, right = r + clev*m 5 reproduction v1 only: left = l + clev*m + 0.707*v1, right = r + clev*m + 0.707v1 6 reproduction v2 only: left = l + clev*m + 0.707*v2, right = r + clev*m + 0.707v2 7 reproduction v1, v2: left = l + clev*m + v1, right = r + clev*m + v2 76543210 value description 0 output as stereo 1 output channel 1 on both output l/r 2 output channel 2 on both output l/r 3 mix channel 1 and 2 to monophonic and output on both l/r 76543210 value description 0 2/0 dolby surround (lt, rt) 1 1/0 (c) 2 2/0 (l, r) 3 3/0 (l, c, r) 4 (l, r, s) 5 3/1 (l, c, r, s) 6 2/2 (l, r, ls, rs - dolby phantom mode 7 3/2 (l, c, r, l s , r s )
STA310 66/90 dolby digital status register audiobaseaddress + 0x76 type: ro software reset: nc hardware reset:und description: this register contains bit stream information extract- ed from the stream. ac3_status1 dolby digital status register 1 address: 0x77 type: ro software reset: nc hardware reset:und description: this register contains bit stream information extract- ed from the stream. ac3_status2 dolby digital status register 2 address + 0x78 type: ro software reset: nc hardware reset:und description: this register contains bit stream information extract- ed from the stream. ac3_status3 dolby digital status register 3 address: 0x79 type: ro software reset: nc hardware reset: und description: this register contains bit stream information extract- ed from the stream. ac3_status4 7 6 5 4321 0 not used fs_cod bitrate code bitfield description bitrate code code identifying the bitrate. bitrate[4..0] = frmsizecod[5..1] fs_cod code identifying the sampling frequency 765432 1 0 reserved lfe acmod bitfield description acmod audio coding mode. indicates which channels are in use. lfe indicates if lfe channel is present in the stream 76543210 bsmod bsid bitfield description bsid bit stream identification, indicates the version of the standard bsmod bbit stream mode, indicates the type of service 765432 1 0 reserved cmixlevel surmixlevel bitfield description cmixlevel downmix level of center channel surmixlevel downmix level of surround channel
67/90 STA310 dolby digital status register 4 address: 0x7a type: ro software reset: nc hardware reset: und description: this register contains bit stream information extract- ed from the stream. ac3_status5 dolby digital status register 5 address : 0x7b type: ro software reset: nc hardware reset: und description: this register contains the code of the language of the audio service, extracted from the stream. ac3_status6 dolby digital status register 6 address:0x7c type: ro software reset: nc hardware reset: und description: this register contains the code indicating the dialog normalization level extracted from the stream. ac3_status7 dolby digital status register 7 address: 0x7d type: ro software reset: nc hardware reset: und description: this register contains bit stream information extract- ed from the stream. 9.17 mpeg configuration registers mp_skip_lfe channel skip address : 0x68 type: r/w software reset: 0x00 hardware reset: und description: 765 4 3 2 1 0 reserved dsurmod copyright origbs lancode bitfield description lancode when at 1, indicates that a language code is provided in the stream origbs when at 1, indicates that the stream is an original copyright when at 1, indicates that the stream is protected by copyright dsurmod in 2/0 mode, indicates if the stream is dolby surround encoded 7654321 0 lancode 76543210 reserved dialog normalization (see dolby specifications) 7654321 0 room type mix level audprodie bitfield description audprodie audprodie: if set, indicates that room type and mix level are provided mix level if audprodie is set, mix level indicates the sound level room type if audprodie is set, mix level indicates the sound level 76543210 reserved
STA310 68/90 when this register is set to 1, the lfe channel is skipped. when this register is set to 0 the lfe chan- nel is decoded (if present). mp_prog_number program numbe r address: 0x69 type: r/w software reset: 0x00 hardware reset: und description: when the stream is in second stereo mode, this reg- ister specifies which program is played. mp_dualmode mpeg setup dual mode addres: 0x6e type: r/w software reset: 0x00 hardware reset: und the mpeg dual_mode is active in downmix mode 1 and 9. mp_drc dynamic range contro l address: 0x6a type: r/w software reset: 0x00 hardware reset: und description; when bit drc=1, dynamic range control is enabled. the dynamic range is set according to the data trans- mitted in the dvd mpeg stream. mp_crc_off crc check off address: 0x6c type: r/w software reset: nc hardware reset: und description: when register is set to 1, the crc in mpeg frame is not checked. when register is set to 0, the crc in mpeg frame is checked if exists. if a crc error oc- curs, the decoder soft mutes the frame (but does not stop). mp_mc_off multi-channel address: 0x6d type: r/w software reset: nc hardware reset: und 7654321 0 reserved prog bitfield description prog select program #0 or #1 where 0: l0,r0 in front channels, 1: l2,r2 in front channels 76543210 value description 0 output as stereo 1 output channel 1 on both outputs l/r 2 output channel 2 on both outputs l/r 3 mix channel 1 and 2 to monophonic, and output on both l/r 7654321 0 drc 76543210 7654321 0 reserved den reserved mc
69/90 STA310 description: mp_downmix mpeg downmix address: 0x6f type: r/w software reset: 0x08 hardware reset: und description: in the table below, l o , r o , c o , ls o , rs o represent the output channels after downmix, and l, r, c, l s , r s are the audio channels. the coefficients k j , k c , k r , k s , depend on the number of input channels. in the above table, the equations are given for a 5 channels input bitstream. if the input bitstream does not contain five channels (l, c, r, l s , r s ), the coefficient kj corresponding to the channel not present is equal to 0. if the mpeg bitstream contains only one surround channel (s), replace (k s x (l s + r s )), (k s x l s and (k s x r s ) by (k s x s) in the above equations. bitfield description mc when mc=1, the multi-channel part of the bitstream is not decoded, only the mpeg-1 compatible bitstream is decoded. bit mc must be set to 1 for an mpeg-1 bitstream. den de-normalization: set den=0 for mpeg1 signals, and set den=1 for mpeg2 multi- channel signals when den=1, mpeg2 multi-channel signals l, c, r, ls and rs can be de-normalized. the signals must first be inverse-weighted then multiplied by the de-normalization factor. this undoes the attenuation carried out at the encoder side to avoid overload when calculating the compatible signals (see mpeg 13818-3 specifications). 7654321 0 value output mode comment 0x00 1/0 (c) = mono c o = k j x l + c + k r x r + k s (l s + r s ) 0x01 2/0 (l, r) = stereo l o = (l + k c x c + k s x l s )/ (1 + k c + k s ), r o = (r + k c x c + k s x r s )/ (1 + k c + k s ) 0x02 3/0 (l, c, r) l o = l + k s x l s , r o = r + k s x r s , c o = c 0x03 2/1 (l, r, s) l o = l + k c x c, r o = r + k c x c, ls o = rs o = k s x (l s + r s ) 0x04 3/1 (l, c, r, s) l o = l, r o = r, c o = c, ls o = rs o = k s x (l s + r s ) 0x05 2/2 (l, r, l s , r s )l o = l + k c x c, r o = r + k c x c, ls o = l s , rs o = r s 0x06 3/2 (l, c, r, l s , r s ) l o = l, r o = r, c o = c, ls o = l s , rs o = r s 0x09 2/0 (dolby surround l t , r t ) l t = (l + 0.707c - 0.707 x 0.5 (ls + r s )) /2.414, r t = (r + 0.707c + 0.707 x 0.5 (l s + r s )) /2.414 0x0a 2/0 karaoke capable: v1 on, v2 on lk = l + 0.707 a1 + 0.707 g, rk = r + 0.707 a2 + 0.707 g 0x0b 2/0 karaoke capable: v1 on, v2 off lk = l + 0.707 a1 + 0.707 g, rk = r + 0.707 g 0x0c 2/0 karaoke capable: v1 off, v2 on lk = l + 0.707 g, rk = r + 0.707 a2 + 0.707 g 0x0d 2/0 karaoke capable: v1 off, v2 off lk = l + 0.707 g, rk = r + 0.707 g 0x0e 2/0 karaoke capable: v1 on, v2 off (dolby digital like) lk = l + 0.707 a1 + 0.707 g, rk = r + 0.707 a1 + 0.707 g 0x0f 2/0 karaoke capable: v1 off, v2 on (dolby digital like) lk = l + 0.707 a2 + 0.707 g, rk = r + 0.707 a2 + 0.707 g 0x1a 3/0 karaoke capable: v1 on, v2 on lk = l + 0.707 a1, ck = g, rk = r + 0.707 a2
STA310 70/90 mp_status0 mpeg status register 0 address : 0x76 type: ro software reset: und hardware reset: und description: mp_status1 mpeg status register 1 address: 0x77 type: ro software reset: und hardware reset: und description: mp_status2 mpeg status register 2 address: 0x78 type: ro software reset: und hardware reset: und description: mp_status3 mpeg status register 3 address : 0x79 type: ro software reset: und hardware reset: und 0x1b 3/0 karaoke capable: v1 on, v2 off lk = l + 0.707 a1, ck = g, rk = r 0x1c 3/0 karaoke capable: v1 off, v2 on lk = l, ck = g, rk = r + 0.707 a2 0x1d 3/0 karaoke capable: v1 off, v2 off lk = l, ck = g, rk = r 0x1e 3/0 karaoke capable: v1 on, v2 off (dolby digital like) lk = l, ck = g + a1, rk = r 0x1f 3/0 karaoke capable: v1 off, v2 on (dolby digital like) lk = l, ck = g + a2, rk = r 7654321 0 id lay[1:0] p bri[3:0] bitfield description bri[3:0] bit rate index p protection bit lay[1:0] layer id identifier 76543210 sfr[1:0] pad pri mod[1:0] mex[1:0] bitfield description mex[1:0] mode extension mod[1:0] mode pri private bit pad padding bit sfr[1:0] sampling frequency 7654321 0 not used c ocb emp[1:0] bitfield description emp[1:0] emphasis rate index ocb original/copy bit c copyright 76543210 cen[1:0] sur[1:0] lfe amx dem[1:0]
71/90 STA310 description: mp_status4 mpeg status register 4 address: 0x7a type: ro software reset: und hardware reset: und description: mp_status5 mpeg status register 5 address: 0x7b type: ro software reset: und hardware reset: und description: the number of extended ancillary data bytes is con- tained in this register 9.18 pink noise generation registers pn_downmix pink noise downmix address: 0x6f type: r/w software reset: nc hardware reset: und description: after this processing, the ocfg stage is applied on these channels. ocfg must be configured to 0 and attenuation on all channels must be set to 10db at- tenuation. the other values must not be used because low fre- quency extraction must not be done when generating pink noise. pink noise selection is made through the stream- sel and decodsel registers. 9.19 pcm beep-tone registers pcm_btone pcm beep tone frequency address: 0x68 bitfield description dem[1:0] dematrix procedure amx audio mix lfe lfe sur[1:0] surround cen[1:0] centre 7654321 0 ext nml[2:0] mfs mly cib cis bitfield description cis copyright id start cib copyright id bit mly multi-lingual layer mfs multi-lingual fs nml[2:0] number of multi-lingual channels ext extension bitstream present 7654321 0 76543210 rs ls lfe c r l bitfield description l 1: left channel contains pink noise 0: left channel is forced to zero r 1: right channel contains pink noise 0: right channel is forced to zero c 1: center channel contains pink noise 0: center channel is forced to zero lfe 1: lfe channel contains pink noise 0: lfe channel is forced to zero ls 1: left surround channel contain pink noise 0: left surround channel is forced to zero rs 1: right surround channel contains pink zero 0: right surround channel is forced to zero 7654321 0
STA310 72/90 type: r/w software reset: 0 hardware reset: und description: the value in this register sets the pcm beep tone fre- quency according to the formula: beep_tone_frequency = (fs/2)/(register_value+1) 9.20 karaoke registers this section describes the registers which select the karaoke effects, for example: volume, chorus, echo, reverb and mute. any change to these registers must be signalled to the dsp by writing 1 to the register. kar_mch0vol music channel 0 (l) volume address: 0x81 type: r/w reset value: 0xff description; this register contains the scaling factor applied to the left channel of the music input. it specifies a fractional multiplication factor whose value varies from 0 to 1.0: music left channel = original music left channel scale_factor. kar_mch1vol music channel 1 (r) volume address: 0x82 type: r/w reset value: 0xff description: this register has the same function as kar_mch0vol for the right music channel. kar_keycont key control (pitch shift) on/off address: 0x83 type: r/w reset value: 0 description: . kar_keyvalue key value address: 0x84 type: r/w reset value: 0x00 description: the pitch shift can be changed from -3.5 to 3.5 tones, in steps of 1/4 tone. this register sets the number of tones according to the following table: 7654321 0 value bitfield description value 0x00: scale factor 0 = left channel mute 0x7f: scale factor 0.5 = half restitution of left channel 0xff: scale factor 1.0 = full restitution of left channel 7654321 0 value 7654321 0 reserved pshift bitfield description pshift 0: pitch shift disabled, 1: pitch shift enabled 7654321 0 keyvalue key control (tone) -1/ 4 -1/ 2 -3/ 4 -1 - 1.1 6 - 1.3 4 - 1.5 8 - 1.9 3 -2.49 -3.5 keyval ue (decimal) 01234567 8 9
73/90 STA310 kar_vcancel voice cancellation on/off address: 0x85 type: r/w reset value: 0 description: kar_vvalue degree of voice cancellation address: 0x86 type: r/w reset value: 0x0 description: when the voice cancellation is enabled by the kar_vcancel register, kar_vvalue specifies the extent of the voice cancellation according to the following table: kar_mmute music channel mute address: 0x87 type: r/w reset value:0 description: this register mutes the music channel. kar_vch0vol voice channel 0 (l) volume address: 0x88 type: r/w reset value: 0xff description: this register has the same function as kar_mch0vol for the left voice channel instead of the left music channel. kar_vch1vol voice channel 1 (r) volume address: 0x89 type: r/w reset value: 0xff description: this register has the same function as kar_mch0vol for the right voice channel instead of the left music channel. key control (tone) 1/4 1/2 3/4 1 1.16 1.34 1.58 1.93 2.49 3.5 keyval ue (decimal) 10 11 12 13 14 15 16 17 18 19 765432 1 0 reserved vcancel bitfield description vcancell 0: voice cancellation off, 1: voice cancellation on 76543210 reserved level[2:0] bitfield description level[2:0] 0: cut-band filter with 40db attenuation at 700hz 1: cut-band filter with 35db attenuation at 700hz 2: cut-band filter with 32db attenuation at 700hz 3: cut-band filter with 27db attenuation at 700hz 4: cut-band filter with 23db attenuation at 700hz 76543210 reserved mute bitfield description mute 0: not muted, 1: muted 76543210 value 76543210 value
STA310 74/90 kar_duet duet on/off switch address: 0x8a type: r/w reset value: 0 description: the value in this register sets the duet function on or off. when selected, the duet function is configured by register kar_duetthresh. kar_duetthresh duet threshold contro l address + 0x8b type: r/w reset delay: 0 description: when the duet function is enabled by the kar_duet register, this register specifies the ampli- tude of the voice line below which the voice is can- celled. if the amplitude of the voice line is below this threshold, the recorded voice is played instead. the value of duetthreshold ranges from 0 to 255, full scale signal. kar_voice selection of voice effects address: 0x8c type: r/w reset delay: 0x0 description: kar_vdelay programmable delay/decay music effects address: 0x8d type: r/w reset value: 0x0 description: the value in this register specifies the delay used for voice input effects. the delay can be set in the range from 0 to 2048/fs seconds (where fs is the sampling frequency in khz). desired time delay = ( 2048 / fs) * ( value / 256) which gives: kar_vdelay value = (fs / 8) * desired time delay for reverberation effects, this register gives the de- cay factor,which can vary within the range 0 to 1.0. kar_vbal programmable mix for echo and chorus effects address: 0x8e type: r/w reset value: 0x3f 7654321 0 reserved duet bitfield description duet 0: duet off and 1: duet on 76543210 duetthreshold[7:0] 76543 2 1 0 reserved mix voiceeff[1:0 ] bitfield description voiceeff selecte the voice effects: 0: no effect is applied to the voice input 1: echo is applied to the voice inputs, tuned by registers kar_vdelay and kar_vbal 2: chorus is applied to the voice inputs, tuned by registers kar_vdelay and kar_vbal 3: reverb is applied to the voice inputs, tuned by register kar_vdelay. mix voice channel mixing: 0: no mix, voice is output on centre channelt 1: mix music and voice channels into music channel. 76543210 value 76543210 balance[7:0]
75/90 STA310 description: this register sets the balance between the original sound and its delayed version for the echo and cho- rus effects according to the formula. echo (or chorus) output = original_sound * (1 - bal- ance) + delayed_sound * balance where balance = balance[7:0] / 255 where balance can vary in the range of 0 to 1. a bal- ance limit of 0.5 is recommended. balance[7:0] = balance * 255. kar_vmute voice channel mute address: 0x8f type: r/w reset value: 0x00 description: this register mutes the voice channel: 0 means not muted and 1 means muted. kar_play mute of voice and music address: 0x90 type: r/w reset value: 0x01 description: this register mutes the voice and the music channels simultaneously: play = 0 means muted and 1 means playing. the registers and kar_vmute have priority for muting. kar_mode operating mode selection address + 0x91 type: r/w reset value: 0x01 description: this register specifies the working mode of the karaoke module. kar_din_ctl control of voice channel address: 0x92 type: r/w reset value: 0x00 description: this register specifies the input format for configuring 7654321 0 reserved mute 76543210 reserved play 765432 1 0 reserved kar_mode[1:0] bitfield description kar_mode [1:0] 00: karaoke processor in waiting mode. this is the default mode after a hardware reset, total or partial software reset. this mode is used to programme all the registers at first initialization. 01: karaoke processor running. 10: partial software reset. this resets the internal dsp program but keep the register configuration as it was before the partial reset. when the partial reset is finished, kar_mode[1:0] is automatically set to 01. 11: total software reset. the program is reset and the registers values are changed back to their reset default values. 7 6 5 43210 reserv ed justif delay ws_p ol clk_p ol ws[1:0] dinen
STA310 76/90 the handling of the second input. kar_update change active karaoke functions address: 0x93 type: r/w reset value: 0 description: this register loads the new karaoke configuration into the internal registers when update is set to 1. when the bit is reset to 0 the system continues in the configuration last loaded. 9.21 second serial input registers sfreq2 sampling frequency of voice channe l address: 0x94 type: ro reset value: 0 description: this register sets the sampling frequency, fs, of the incoming pcm stream. caninput_mode selection of input data forma t address: 0x95 type: r/w reset value: 0x00 description; this register specifies the input format for configuring the handling of the second input. 9.22 linear pcm (dvd audio) registers lpcma_downmix downmix address : 0x6f type: r/w software reset: nc bitfield description dinen din enable: 0: disabled, 1: enabled ws[1:0] pcm precision: 00: 16-bit mode, 01: 18-bit mode, 10: 20-bit mode, 11: 24-bit mode clk_pol 0: data and ws change on clockalling edge 1: data and ws change on clockising edge ws_pol 0: left data word = ws low, right data word = ws high 1: left data word = ws high, right data word = ws low delay 0: first bit of data occurs on transition of ws 1: first bit of data occurs with 1 clock cycle delay (i2s compatible) justif 0: left padded, 1: right padded 7654321 0 reserved update 76543210 reserved value fs (khz) 48 44.1 32 - 96 88.2 64 - 24 22.05 value (decimal) 0123456789 fs (khz) 16 - 12 11.02 5 8 - 192 176.4 128 - value (decimal) 10 11 12 13 14 15 16 17 18 19 76543210 swap mode[6;0] bitfield description mode [6:0] 0: 16 slots mode 1: 16 slots mode, lsb first 2: 32 slots mode, left aligned 3: 32 slots mode, right aligned 4: 32 slots mode, i2s mode 5: 32 slots mode, sign extended 6: 32 slots mode, 8-bit data 7: 32 slots mode16-bit data swap channel swap: 0: left channel first, 1: right channel firs 76543210 reserved value
77/90 STA310 hardware reset: und description;:. the notation, 2/0 represents 2 front speakers and no surround speakers. lpcma_force_dws downsampling 192 to 96khz address : 0x70 type: r/w software reset: nc hardware reset: und description: this register selects whether downsampling is used for input streams requiring sampling frequencies of 192khz or 176.4khz. when automatic is selected, register is automatically updated to correspond to the new output frequency. lpcma_dm_coeft_0 downmix phase coefficients 0 address : 0x97 type: r/w software reset: nc hardware reset: und description: this register sets the phase coefficients for channels mixing to lmix. the input signal is inverted when ph_xl = 0 and non-inverted when 1. lpcma_dm_coeft_1 downmix phase coefficients 1 address: 0x98 type: r/w software reset: nc hardware reset: und description: this register sets the phase coefficients for channels mixing to rmix. the input signal is inverted when ph_xr = 0 and non-inverted when 1. lpcma_dm_coeft_2 downmix gain coefficients 2 address: 0x99 type: r/w software reset: nc hardware reset: und description: this register sets the mixing gain for lf to lmix. see the note after register lpcma_dm_coeft_3 downmix gain coefficients 3 address : 0x9a type: r/w software reset: nc value description 0 downmix not applied 1 force downmix 2/0 2 downmix 2/0 is applied if the flags down_mix_code_validity and stereo_playback_mode are both 0 in the bitstream 76543210 reserved value bitfield description value 00: automatic (if fs = 192khz or 176.4khz) 01: automatic (if fs = 192khz or 176.4khz) 10: no downsampling 76543210 0 ph_1l ph_2l ph_3l ph_4l ph_5l reserved 76543210 ph_0r 0 ph_2r ph_3r ph_4r ph_5r reserved 7654321 0 coef_0l 7654321 0 coef_0r
STA310 78/90 hardware reset: und description: this register sets the mixing gain for lf to rmix. see the note after register lpcma_dm_coeft_4 downmix gain coefficients 4 address: 0x9b type: r/w software reset: nc hardware reset: und description: this register sets the mixing gain for rf to lmix. see the note after register lpcma_dm_coeft_13. lpcma_dm_coeft_5 downmix gain coefficients 5 address: 0x9c type: r/w software reset: nc hardware reset: und description: this register sets the mixing gain for rf to rmix. see the note after register lpcma_dm_coeft_13. lpcma_dm_coeft_6 downmix gain coefficients 6 address: 0x9d type: r/w software reset: nc hardware reset: und description: this register sets the mixing gain for c to lmix. see the note after register . lpcma_dm_coeft_7 downmix gain coefficients 7 address: 0x9e type: r/w software reset: nc hardware reset: und description: this register sets the mixing gain for c to rmix. see the note after register lpcma_dm_coeft_8 downmix gain coefficients 8 address: 0x9f type: r/w software reset: nc hardware reset: und description: this register sets the mixing gain for ls / s to lmix. see the note after register lpcma_dm_coeft_9 downmix gain coefficients 9 address : 0xa0 type: r/w software reset: nc 7654321 0 coef_1l 7654321 0 coef_1r 7654321 0 coef_2l 7654321 0 coef_2r 7654321 0 coef_3l 7654321 0 coef_3r
79/90 STA310 hardware reset: und description: this register sets the mixing gain for ls / s to rmix. see the note after register lpcma_dm_coeft_10 downmix gain coefficients 10 address : 0xa1 type: r/w software reset: nc hardware reset: und description: this register sets the mixing gain for rs to lmix. see the note after register . lpcma_dm_coeft_11 downmix gain coefficients 11 address: 0xa2 type: r/w software reset: nc hardware reset: und description: this register sets the mixing gain for rs to rmix. see the note after register lpcma_dm_coeft_12 downmix gain coefficients 12 address: 0xa3 type: r/w software reset: nc hardware reset: und this register sets the mixing gain for lfe to lmix. see the note after register . lpcma_dm_coeft_13 downmix gain coefficients 13 address: 0xa4 type: r/w software reset: nc hardware reset: und description: this register sets the mixing gain for lfe to rmix note: for dvd audio, the real coefficient value, alpha[x], applied to channel x is calculated with the following formulae: alpha[x] = 2 -(coef_xl/30) 0 STA310 80/90 address: 0x77 type: ro software reset: nc hardware reset: und description: this register contains bit stream information extract- ed from the stream. lpcma_status2 linear pcm (dvd audio) status register address: 0x78 software reset: nc hardware reset: und description: this register contains bit stream information extract- ed from the stream. lpcma_status3 linear pcm (dvd audio) status register address: 0x79 type: ro software reset: nc hardware reset: und description: this register contains bit stream information extract- ed from the stream. lpcma_status4 linear pcm (dvd audio) status register address: 0x7a type: ro software reset: nc hardware reset: und description: this register contains bit stream information extract- ed from the stream. lpcma_status5 linear pcm (dvd audio) status register address: 0x7b type: ro software reset: nc hardware reset: und description: this register contains information, extracted from the stream, for the dynamic range control. bitfield description quantization_word _length_2[3:0] quantization word length for group 2 quantization_word _length_1[3:0] quantization word length for group 1 7654321 0 sampling_frequency _1[3:0] sampling_frequency_ 2[3:0] bitfield description sampling_frequ ency_2[3:0] sampling frequency for group 2 sampling_frequ ency_1[3:0] sampling frequency for group 1 7654 3 2 1 0 reserved multi_channel_type[3:0] bitfield description multi_channel_type[3:0] 7654321 0 bit_shift_of_channel _gr2[3:0] channel_assignment [3:0] bitfield description channel_assignment[3:0] bit_shift_of_channel_gr2[3:0] 7654321 0 dynamic_range_control[7:0]
81/90 STA310 9.23 linear pcm (dvd video and pcm) registers lpcmv_downmix downmix address : 0x6f type: r/w software reset: nc hardware reset: und description;. the notation, 2/0 represents 2 front speakers and no surround speakers. lpcmv_force_dws downsampling 96 to 48khz address: 0x70 type: r/w software reset: nc hardware reset: und description: this register selects whether downsampling is used for input streams requiring a sampling frequency of 96khz. when automatic is selected, register is automatical- ly updated to correspond to the new output frequen- cy. lpcmv_dm_coeft_0 downmix phase coefficients 0 address: 0x97 type: r/w software reset:nc hardware reset: und description: this register sets the phase coefficients for channels mixing to lmix. the input signal is inverted when ph_xl = 0 and non-inverted when 1. lpcmv_dm_coeft_1 downmix phase coefficients 1 address: x98 type: r/w software reset:nc hardware reset: und description: this register sets the phase coefficients for channels mixing to rmix. the input signal is inverted when ph_xr = 0 and non-inverted when 1. lpcmv_dm_coeft_2 downmix gain coefficients 2 for details see register 0x99 lpcmv_dm_coeft_3 downmix gain coefficients 3 for details see register 0x9a lpcmv_dm_coeft_4 downmix gain coefficients 4 for details see register 0x9b 7654321 0 reserved value value description 0 downmix not applied 1 force downmix 2/0 76543210 reserved value bitfield description value 00: automatic (if fs = 96khz) 01: automatic (if fs = 96khz) 10: no downsampling 76543210 ph_0l ph_1l ph_2l ph_3l ph_4l ph_5l reserved 76543210 ph_0r ph_1r ph_2r ph_3r ph_4r ph_5r reserved
STA310 82/90 lpcmv_dm_coeft_5 downmix gain coefficients 5 for details see register 0x9c pcmv_dm_coeft_6 downmix gain coefficients 6 for details see register 0x9d lpcmv_dm_coeft_7 downmix gain coefficients 7 for details see register 0x9e lpcmv_dm_coeft_8 downmix gain coefficients 8 for details see register 0x9f lpcmv_dm_coeft_9 downmix gain coefficients 9 for details see register 0xa0 pcmv_dm_coeft_10 downmix gain coefficients 10 for details see register 0xa1 lpcmv_dm_coeft_11 downmix gain coefficients 11 for details see register 0xa2 lpcmv_dm_coeft_12 downmix gain coefficients 12 for details see register 0xa3 lpcmv_dm_coeft_13 downmix gain coefficients 13 for details see register 0xa4 note: for dvd video & pcm, the real coefficient value, alpha[x], ap- plied to channel x is calculated with the following formulae: alpha[x] = 2-(x+(y/30)) 0 83/90 STA310 pcmv_status2 address : 0x78 type: rw reset value: und description: this register sets the dynamic range compression from the first access unit. for the hexadecimal value 0x80, dynamic range control is not set. for all other values, the dynamic range control is (24.082 - 6.0206 * x - 0.2007 * y)db, where x = dynamic_range_control[7..5] and y = dynamic_range_control[4..0]. lpcmv_ch_assign channel assignment address: 0xa8 type: r/w software reset: nc hardware reset: und description: pcmv_multi_chs multi channels address: 0xa9 type: r/w software reset: nc hardware reset: und description: 9.24 mlp registers mlp_crc crc check address: 0x6c type: r/w software reset: nc hardware reset: und description: this register controls the four different crcs in mlp. if the check is false, an error is returned (error num- bers 80-83 in register and the outputs of all 6 chan- nels are muted mlp_downmix downmix address: 0x6f type: r/w software reset: nc hardware reset: und 76543210 dyn_range_control 76543210 reserved value value description value (decimal) this register configures the audio channels: see "dvd specifications for read-only disc", part 4 audio specifications, version 1.0, march 1999, table c.1-2. 7654321 0 reserved value value description value (decimal) this register configures the multi channel structure for the output channels: 0: stereo 1: multi channels 7654 3 2 1 0 reserved su_p ma_s ms_c rh_c bitfield description rh_c 1: check of restart_header_crc enable ms_c 1: check of major_sync_crc enable ma_c 1: check of max_shift enable su_p 1: check of substream_parity enable 76543210 dwnmix[7:0]
STA310 84/90 description: this register controls the mlp downmix. mlp_drc dynamic range control address : 0x6a type: r/w software reset: nc hardware reset:: und description: when this register = 0x00, the dynamic range control is disabled. when 0x01, the dynamic range control is enabled and the drc information in the mlp stream is used. mlp_force_dws downsampling 192 to 96khz or 176.4 to 88.2khz address: 0x70 type: r/w software reset: nc hardware reset: und description: this register selects whether downsampling is used for input streams requiring sampling frequencies of 192khz or 176.4khz. when automatic is selected, register is automatically updated to correspond to the new output frequency. mlp_lfe decode lfe address: 0x68 type: r/w software reset: nc hardware reset: und description: when this register = 0x00, lfe is not decoded and when 0x01, lfe is decoded. mlp_status0 mlp status 0 register address: 0x76 type: r/w software reset: nc hardware reset: und type: this status register contains the sampling frequency codes.. bitfield description dwnmix [7:0] 0x00: 2/0 (l / r) 0x01: 2/0 (a) (lo / ro) (according to bitstream0) 0x02: 3/0 (l, r, c) 0x03: 2/1 (l, r, s) 0x04: 3/1 (l, c, r, s) 0x05: 2/2 (l, r, ls, rs) 0x06: 3/3 (l, c, r, ls, rs) for all other values there is no downmix. (a) downmix 1/0 (one channel only) is forbidden in dvd audio 76543210 drc[7:0] 7654321 0 reserved value bitfield description value 00: automatic (if fs = 192khz or 176.4khz) 01: automatic (if fs = 192khz or 176.4khz) 10: no downsampling 76543210 lfe[7:0] 76543210 reserved fs_code[4:0] bitfield description fs_cod e[4:0] this list gives the codes and the corresponding sampling frequency. 0x09: 44.1khz 0x0a: 48khz 0x0d: 88.2khz 0x0e: 96khz 0x11: 176.4khz 0x12: 192khz 0x1f: undefined the remaining codes are reserved.
85/90 STA310 mlp_status1 mlp status 1 register address : 0x77 type: ro software reset: nc hardware reset: und description: this status register contains the channel assignment. mlp_status2 mlp status 2 register address: 0x78 type: ro software reset: nc hardware reset: und description: this status register contains the number of sub- streams present in the audio frame. mlp_status3 mlp status 3 register address: : 0x79 type: ro software reset: nc hardware reset: und description: this status register contains the sub-stream informa- tion codes.. 9.25 de-emphasis register deemph de-emphasis address: 0xb5 type: r/ws software reset: nc hardware reset: und description: this register is used in mpeg, dvd_lpcm or cdda modes; it is not supported in dolby digital. in mpeg and dvd_lpcm modes, its register value is extracted from the bitstream. when the emphasis status changes (by setting bit dem of the register), an interrupt is generated. in cdda mode, the register value must be updated by the application. the de-emphasis filter specified here is applied only if bit dem of the register is set. 9.26 auxilliary outputs registers vcr_mix vcr outputs 76543210 reserved ch_assign[4:0] bitfield description ch_ass ign[4:0] this gives the channel assignment: see "dvd specifications for read-only disc", part 4 audio specifications, version 1.0, march 1999, table c.1-1. 76543 2 1 0 reserved nsubstr[3:0] 7654321 0 reserved substr_code[3:0] bitfield description substr_code [3:0] 2-channel decoder: bit0 = 1: sub-stream 0 is decoded bit1 = 1: a simplified decoder can be used for sub-stream 0 6-channel decoder: bit2 = 1: sub-stream 0 is decoded bit3 = 1: sub-stream 1 is decoded 7654321 0 reserved d[1:0] bitfield description d[1:0] 00: none, 01: 50/15s, 10: reserved, 11: ccitt j.17 7654 321 0 reserved stereo prl reserved copy 3d_vcr
STA310 86/90 address: 0xae type: r/ws?? software reset: nc hardware reset: 0 description: note: 1. to have both "3-d sound" on the "vcr" and "left/right" channels, the setup is: vcr_mix = 0x02 and pdec = 0x40 for srs process- ing, vcr_ldly vcr left channel delay address: 0xaf type: r/ws?? software reset: nc hardware reset: 0 description: this register contains the vcr left channel delay val- ue. see note after next register description. vcr_rdly vcr right channel delay address: 0xaf type: r/ws?? software reset: nc hardware reset: 0 description: this register contains the vcr right channel delay value. the values for left_vcr_delay and right_vcr_delay are taken into account only when register.bit .dly = 1. 9.27 miscellaneous breakpoint to be defined address + 0x2b type: r/w software reset: nc hardware reset: 0 description: this register must be set to 0x08. clockcmd to be defined address: 0x3a type: r/w software reset: nc hardware reset: 0 description: this register must be set to 0x00. bitfield description 3d_vcr this bit selects "3-d sound" on the vcr channels using srs processing (depending on the pdec registers and ): 0: standard sound (disable "3-d sound"), 1: enable "3-d sound". copy this bit is used to copy "left/right" channels to "vcr" channels: 0: no copy, 1: copy enable. prl this bit enables a "prologic downmix" on the "vcr" channels: 0: disable, 1: enable. stereo this bit enables a "2/0 downmix" on the "vcr" channels: 0: disable, 1: enable. 7654321 0 left_vcr_delay 76543210 right_vcr_delay 7654321 0 reserved 76543210 reserved
87/90 STA310 i nit_ram ram initialization address : 0xff type: ro software reset: 1 hardware reset: 0 description: the register is used to signal when the STA310 has finished to boot. after a soft reset or a hardware reset, or a hardware reset, the host processor must wait until init_ram hold the value 1. the host can then start to configure the STA310 according to its application appendix a overview of the chip this STA310 is based on a very high performances low power general purpose dsp core, mmdsp+, and a set of dedicated peripherals. internal audio and system pll allows to configure the chip for a wide range of audio frequencies and dsp processing power (1 to 100 mips). a.1 architectural block diagram 7654321 0 reserved ram_init st asdsp xbus ybus emulation 18kx24 rom 15kx24 ram 32 kinstr rom s/pdif in i2s packet parser frame buffer 32k x 8 parallel audio parser dbit/nbit dma x 3 pcm rs232 data in host 256x8 host registers sys pll in in/out slave data in rs232 line control 8 channels pcm output s/pdiff out 1ws mem audio pll two mmdsp+ core parallel i2c 64kx8 2048 bits input fifo crc checkers 256x24 ram 768words ram s/pdiff out 4x2 out cna interf i2s/sony dma 4kx16 ram second serial input i2sin
STA310 88/90 a.2 description of the architecture the mmdsp+ dsp core can access 5 banks of ram/rom memories: - the 32k instruction rom, - the 768 words instruction development ram, - x_memory 19k x 24 ram, - y_memory 18 k x 24 rom, - y_memory 1k x 24 ram. the dsp core can also access some dedicated and general purpose peripherals. these peripherals (called mmio peripherals) are mapped as memory locations of the x memory space of the mmdsp+ dsp core. on top of the front-end dedicated ones, the list of the peripherals is the following: - four pcm out i2s/sony (16,18,20,24 bits) serial output interfaces are provided to connect, typically, to external dacs. this interface and the audio pll provide the oversampling clocks and the serial clocks necessary to interface the dacs .this interface provides up to 8 independent audio channels. a dma pcm mmio block makes the link between the x data memory of the dsp core (which can store the audio samples) and the i2s/sony serial interfaces. this mmio block is a dma (direct mem- ory access) and handles automatically the transfer of data by blocks. this peripheral implements also an hardware mechanism to support delayed channels. each channel can de delayed (resolution 1 sample) by a programmable number of data samples. this function is totally transparent to the user. - a 256 x 8 address space is shared between the mmdsp+ core (as mmio peripheral) and the external world of the STA310 through the i2c slave interface or the host parallel interface. this area is divided mainly in 2 parts: a 192 x 8 general purpose ram area, a 64 x (1 to 8 bits) area of specific registers. - the two plls (audio pll and system pll) can be controlled by the dsp itself (thru the mmio bus) or by the external world of the STA310 (thru the i2c slave i/f or the host parallel i/f).
89/90 STA310 dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.22 0.32 0.38 0.009 0.013 0.015 c 0.09 0.20 0.003 0.008 d 16.00 0.630 d1 14.00 0.551 d3 12.35 0.295 e 0.65 0.0256 e 16.00 0.630 e1 14.00 0.551 e3 12.35 0.486 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.0393 k3.5 (min.), 7 (max.) tqfp80 (14x14x1.40mm) a a2 a1 seating plane c 20 21 40 41 60 61 80 e3 d3 e1 e d1 d e 1 b tqfp80l 0.10mm .004 pin 1 identification k l l1 0.25mm gage plane outline and mechanical data
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan -malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states. http://www.st.com 90/90 STA310

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